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document number: mmpf0200 rev. 6.0, 8/2016 nxp semiconductors data sheet: adva nce information * this document contains cert ain information on a new product. specifications and information herein are subject to change without notice. ? 2016 nxp b.v. 12 channel configurable power management integrated circuit the pf0200 power management integrated circuit (pmic) provides a highly programmable/ configurable architecture , with fully integrated power devices and minimal external components. with up to four buck converters, one boost regulator, six linear regulators, rtc supply, and coin-cell charger, the pf0200 can provide power for a complete system , including applications processors, memory, and system peripherals, in a wi de range of applicat ions. with on-chip one time programmable (otp) memory, the pf0200 is available in pre- programmed standard versions, or non-programmed to support custom programming. the pf0200 is especially suited to the i.mx 6sololite, i.mx 6solo and i.mx 6duallite versions of the i.mx 6 family of devices and is supported by full system level reference designs, and pre-programmed versions of the device. this device is powered by smartmos technology. features: ? three to four buck converters, depending on configuration ? boost regulator to 5.0 v output ? six general purpose linear regulators ? programmable output volt age, sequence, and timing ? otp (one time programmable) me mory for device configuration ? coin cell charger and rtc supply ? ddr termination reference voltage ? power control logic with processor interface and event detection ?i 2 c control ? individually programmable on, off, and standby modes figure 1. simplified application diagram power management pf0200 ep suffix (e-type) 56 qfn 8x8 98asa00405d applications ?tablets ?iptv ? industrial control ? medical monitoring ? home automation/ alarm/ energy management es suffix (wf-type) 56 qfn 8x8 98asa00589d vgen3 vgen5 camera audio codec cluster/hud external amp microphones speakers front usb pod rear usb pod rear seat infotaiment sensors i.mx6x i 2 c communication i 2 c communication pf0200 control signals parallel control/gpios licell charger coincell main supply vgen1 vgen2 vgen4 vgen6 swbst sw3a/b sw1a/b sw2 gps mipi upcie sata - flash nand - nor interfaces processor core voltages camera vrefddr ddr memory ddr memory interface sd-mmc/ nand mem. sata hdd wam gps mipi hdmi ldvs display usb ethernet can
2 nxp semiconductors pf0200 table of contents 1 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 16 mhz and 32 khz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 control interface i2c block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.2 pf0200 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.1 packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
nxp semiconductors 3 pf0200 orderable parts 1 orderable parts the pf0200 is available with both pre-programmed and non-progr ammed otp memory configurations. the non-programmed device uses ?np? as the programming code. the pre-programmed devices are ident ified using the program codes from table 1 , which also list the associated nxp reference designs where applicable. details of the otp programming for each device can be found in table 8 . contact your nxp representative for more details. table 1. orderable part variations part number temperature (t a ) package programming reference designs qualification tier notes mmpf0200npaep -40 to 85 c 56 qfn 8x8 mm - 0.5 mm pitch e-type qfn (full lead) np n/a consumer (2)(1) MMPF0200F0AEP f0 n/a (2)(1) mmpf0200f3aep f3 n/a (2)(1) mmpf0200f4aep f4 n/a (2)(1) mmpf0200f6aep f6 i.mx6sx-sdb (2)(1) mmpf0200f0anes -40 to 105 c 56 qfn 8x8 mm - 0.5 mm pitch wf-type qfn (wettable flank) f0 n/a extended industrial (2)(1) mmpf0200f3anes f3 n/a (2)(1) mmpf0200f4anes f4 n/a (2)(1) notes 1. for tape and reel add an r2 suffix to the part number. 2. for programming details see table 8 .
4 nxp semiconductors pf0200 internal block diagram 2 internal block diagram figure 2. pf0200 simplified internal block diagram vin intb licell swbstfb swbstin swbstlx o/p drive swbst 600 ma boost pwron standby ictest scl sda vddio sw3a/b single phase 2500 ma buck vcoredig vcoreref sdwnb gndref sw1ain sw1fb sw1alx sw1blx sw1a/b single/dual 2500 ma buck vsnvs vsnvs li cell charger resetbmcu sw2 1500 ma buck vgen1 100 ma vgen1 vin1 vgen2 250 ma vgen2 vgen3 100 ma vgen3 vin2 vgen4 350 ma vgen4 vgen5 100 ma vgen5 vin3 vgen6 200 ma vgen6 best of supply otp vrefddr vddotp vinrefddr vhalf vcore pf0200 control clocks 32 khz and 16 mhz initialization state machine i 2 c interface clocks and resets i 2 c register map trim-in-package o/p drive o/p drive sw1bin sw2fb sw2lx o/p drive sw2in sw2in sw3ain sw3afb sw3alx sw3blx o/p drive o/p drive sw3bin sw3bfb sw3vsssns supplies control dvs control dvs control reference generation core control logic gndref1 sw1vsssns rsvd1 rsvd2 rsvd3 rsvd4 rsvd5 rsvd6
nxp semiconductors 5 pf0200 pin connections 3 pin connections 3.1 pinout diagram figure 3. pinout diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 43 44 45 46 47 48 49 50 51 52 53 54 55 56 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 intb sdwnb resetbmcu standby ictest sw1fb sw1ain sw1alx sw1blx sw1bin rsvd1 rsvd2 rsvd3 sw1vsssns licell vgen6 vin3 vgen5 sw3afb sw3ain sw3alx sw3blx sw3bin sw3bfb sw3vsssns vrefddr vinrefddr vhalf pwron vddio scl sda vcoreref vcoredig vin vcore gndref vddotp swbstlx swbstin swbstfb vsnvs gndref1 vgen1 vin1 vgen2 rsvd4 rsvd5 rsvd6 sw2lx sw2in sw2in sw2fb vgen3 vin2 vgen4 ep
6 nxp semiconductors pf0200 pin connections 3.2 pin definitions table 2. pf0200 pin definitions pin number pin name pin function max rating type definition 1 intb o 3.6 v digital open drain interrupt signal to processor 2 sdwnb o 3.6 v digital open drain signal to indicate an imminent system shutdown 3 resetbmcu o 3.6 v digital open drain reset output to processor. alternatively can be used as a power good output. 4 standby i 3.6 v digital standby input signal from processor 5 ictest i 7.5 v digital/ analog reserved pin. connect to gnd in application. 6sw1fb (4) i 3.6 v analog output voltage feedback for sw1a/b. route this trace separately from the high- current path and terminate at the output capacitance. 7sw1ain (4) i 4.8 v analog input to sw1a regulator. by pass with at least a 4.7 f ceramic capacitor and a 0.1 f decoupling capacitor as cl ose to the pin as possible. 8 sw1alx (4) o 4.8 v analog regulator 1a switch node connection 9 sw1blx (4) o 4.8 v analog regulator 1b switch node connection 10 sw1bin (4) i 4.8 v analog input to sw1b regulator. by pass with at least a 4.7 f ceramic capacitor and a 0.1 f decoupling capacitor as cl ose to the pin as possible. 11 rsvd1 - - reserved reserved for pin to pin compatibility. internally connected. leave this pin unconnected. 12 rsvd2 - - reserved reserved for pin to pin compatibility. connect this pin to vin. 13 rsvd3 - - reserved reserved for pin to pin compatibility. internally connected. leave this pin unconnected. 14 sw1vsssns gnd - gnd ground reference for regulator sw1ab. it is connected exter nally to gndref through a board ground plane. 15 gndref1 gnd - gnd ground reference for regulator sw2. it is connected externally to gndref, via board ground plane. 16 vgen1 o 2.5 v analog vgen1 regulator output, bypass with a 2.2 f ceramic output capacitor. 17 vin1 i 3.6 v analog vgen1, 2 input supply. bypass with a 1.0 f decoupling capacitor as close to the pin as possible. 18 vgen2 o 2.5 v analog vgen2 regulator output, bypass with a 4.7 f ceramic output capacitor. 19 rsvd4 - - reserved reserved for pin to pin compatibility. internally connected. leave this pin unconnected. 20 rsvd5 - - reserved reserved for pin to pin compatibility. connect this pin to vin 21 rsvd6 - - reserved reserved for pin to pin compatibility. internally connected. leave this pin unconnected. 22 sw2lx (4) o 4.8 v analog regulator 2 switch node connection 23 sw2in (4) i 4.8 v analog input to sw2 regulator. connect pin 23 together with pin 24 and bypass with at least a 4.7 f ceramic capacitor and a 0.1 f decoupling capacitor as close to these pins as possible. 24 sw2in (4) i 4.8 v analog 25 sw2fb (4) i 3.6 v analog output voltage feedback for sw2. route this trace separately from the high-current path and terminate at the output capacitance. 26 vgen3 o 3.6 v analog vgen3 regulator output. bypass with a 2.2 f ceramic output capacitor. 27 vin2 i 3.6 v analog vgen3,4 input. bypass with a 1.0 f decoupling capacitor as close to the pin as possible.
nxp semiconductors 7 pf0200 pin connections 28 vgen4 o 3.6 v analog vgen4 regulator output, bypass with a 4.7 f ceramic output capacitor. 29 vhalf i 3.6 v analog half supply reference for vrefddr 30 vinrefddr i 3.6 v analog vrefddr regulator input. bypass with at least 1.0 f decoupling capacitor as close to the pin as possible. 31 vrefddr o 3.6 v analog vrefddr regulator output 32 sw3vsssns gnd - gnd ground reference for the sw3 regulator. c onnect to gndref externally via the board ground plane. 33 sw3bfb (4) i 3.6 v analog output voltage feedback for sw3b. route this trace separately from the high-current path and terminate at the output capacitance. 34 sw3bin (4) i 4.8 v analog input to sw3b regulator. bypass with at least a 4.7 f ceramic capacitor and a 0.1 f decoupling capacitor as close to the pin as possible. 35 sw3blx (4) o 4.8 v analog regulator 3b switch node connection 36 sw3alx (4) o 4.8 v analog regulator 3a switch node connection 37 sw3ain (4) i 4.8 v analog input to sw3a regulator. bypass with at least a 4.7 f ceramic capacitor and a 0.1 f decoupling capacitor as close to the pin as possible. 38 sw3afb (4) i 3.6 v analog output voltage feedback for sw3a. route this trace separately from the high-current path and terminate at the output capacitance. 39 vgen5 o 3.6 v analog vgen5 regulator output. bypass with a 2.2 f ceramic output capacitor. 40 vin3 i 4.8 v analog vgen5, 6 input. bypass with a 1.0 f decoupling capacitor as close to the pin as possible. 41 vgen6 o 3.6 v analog vgen6 regulator output. by pass with a 2.2 f ceramic output capacitor. 42 licell i/o 3.6 v analog coin cell supply input/output 43 vsnvs o 3.6 v analog ldo or coin cell output to processor 44 swbstfb (4) i 5.5 v analog boost regulator feedback. connect this pin to the output rail close to the load. keep this trace away from ot her noisy traces and planes. 45 swbstin (4) i 4.8 v analog input to swbst regulator. by pass with at least a 2.2 f ceramic capacitor and a 0.1 f decoupling capacitor as close to the pin as possible. 46 swbstlx (4) o 7.5 v analog swbst switch node connection 47 vddotp i 10 v (3) digital & analog supply to program otp fuses 48 gndref gnd - gnd ground reference for the main band gap regulator. 49 vcore o 3.6 v analog analog core supply 50 vin i 4.8 v analog main chip supply 51 vcoredig o 1.5 v analog digital core supply 52 vcoreref o 1.5 v analog main band gap reference 53 sda i/o 3.6 v digital i 2 c data line (open drain) 54 scl i 3.6 v digital i 2 c clock 55 vddio i 3.6 v analog supply for i 2 c bus. bypass with 0.1 f decoupling capacitor as close to the pin as possible. 56 pwron i 3.6 v digital power on/off from processor table 2. pf0200 pin definitions (continued) pin number pin name pin function max rating type definition
8 nxp semiconductors pf0200 pin connections - ep gnd - gnd expose pad. functions as ground return for buck regulators. tie this pad to the inner and external ground planes through vias to allow effective thermal dissipation. notes 3. 10 v maximum voltage rating during otp fuse prog ramming. 7.5 v maximum dc voltage rated otherwise. 4. unused switching regulators should be c onnected as follow: pins swxlx and swxfb s hould be unconnected and pin swxin should be connected to vin with a 0.1 f bypass capacitor. table 2. pf0200 pin definitions (continued) pin number pin name pin function max rating type definition
nxp semiconductors 9 pf0200 general product characteristics 4 general product characteristics 4.1 absolute maximum ratings table 3. absolute maximum ratings all voltages are with respect to ground, unle ss otherwise noted. exceeding these rating s may cause malfunction or permanent dam age to the device. the detailed maximum voltage rating per pin can be found in the pin list section. symbol description value unit notes electrical ratings v in main input supply voltage -0.3 to 4.8 v v ddotp otp programming input supply voltage -0.3 to 10 v v licell coin cell voltage -0.3 to 3.6 v v esd esd ratings human body model charge device model 2000 500 v (5) notes 5. esd testing is performed in accordance with t he human body model (hbm) (czap = 100 pf, rzap = 1500 ), and the charge device model (cdm), robotic (czap = 4.0 pf).
10 nxp semiconductors pf0200 general product characteristics 4.2 thermal characteristics 4.2.1 power dissipation during operation, the temperature of the die should not exceed the operating junction temperature noted in table 4 . to optimize the thermal management and to avoid overheating, the pf0200 provides t hermal protection. an internal comparator monitors the die temperature. interrupts therm110i, therm120i, therm125i, and therm130i will be generated when the respective thresholds specified in table 5 are crossed in either direction. the temperature range can be determined by reading the thermxxxs bits in register intsense0. in the event of excessive power dissipation, thermal protection circuitry will shut down the pf020 0. this thermal protection wi ll act above the thermal protection threshold listed in table 5 . to avoid any unwanted power downs resultin g from internal noise, the protection is debounced for 8.0 ms. this protection should be considered as a fail-safe mechanism and therefore the system should be configured such that this protection is not tripped under normal conditions. table 4. thermal ratings symbol description (rating) min. max. unit thermal ratings t a ambient operating temperature range pf0200a pf0200an -40 -40 85 105 c t j operating junction temperature range -40 125 c (6) t st storage temperature range -65 150 c t pprt peak package reflow temperature ? note 8 c (7)(8) qfn56 thermal resistance and package dissipation ratings r ja junction to ambient natural convection four layer board (2s2p) eight layer board (2s6p) ? ? 28 15 c/w (9)(10)(11) r jma junction to ambient (@200 ft/min) four layer board (2s2p) ? 22 c/w (9)(11) r jb junction to board ? 10 c/w (12) r jcbottom junction to case bottom ? 1.2 c/w (13) jt junction to package top natural convection ? 2.0 c/w (14) notes 6. do not operate beyond 125 c for extended periods of time. operation above 150 c may cause permanent damage to the ic. see table 5 for thermal protection features. 7. pin soldering temperature limit is for 10 seconds maximum du ration. not designed for immersion soldering. exceeding these lim its may cause a malfunction or permanent damage to the device. 8. nxp?s package reflow capability meets pb-free requirements fo r jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core i d to view all orderable parts (i.e. mc33xxxd ent er 33xxx), and review parametrics. 9. junction temperature is a function of di e size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 10. the board uses the jedec specifications for th ermal testing (and simulation) jesd51-7 and jesd51-5. 11. per jedec jesd51-6 with the board horizontal. 12. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the to p surface of the board near the package. 13. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1 ). 14. thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature pe r jedec jesd51- 2. when greek letters are not available, the therma l characterization parameter is written as psi-jt.
nxp semiconductors 11 pf0200 general product characteristics 4.3 electrical characteristics 4.3.1 general specifications table 5. thermal protection thresholds parameter min. typ. max. units notes thermal 110 c threshold (therm110) 100 110 120 c thermal 120 c threshold (therm120) 110 120 130 c thermal 125 c threshold (therm125) 115 125 135 c thermal 130 c threshold (therm130) 120 130 140 c thermal warning hysteresis 2.0 ? 4.0 c thermal protection threshold 130 140 150 c table 6. general pmic static characteristics consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, vin = 2.8 to 4.5 v, v ddio = 1.7 to 3.6 v, typical external component values and full load curre nt range, unless otherwise noted. pin name parameter load condition min. max. unit pwron v il ? 0.0 0.2 * v snvs v v ih ? 0.8 * v snvs 3.6 v resetbmcu v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7* v in vin v scl v il ? 0.0 0.2 * v ddio v v ih ? 0.8 * v ddio 3.6 v sda v il ? 0.0 0.2 * v ddio v v ih ? 0.8 * v ddio 3.6 v v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7*v ddio v ddio v intb v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7* v in v in v sdwnb v ol -2.0 ma 0.0 0.4 v v oh open drain 0.7* v in v in v standby v il ? 0.0 0.2 * v snvs v v ih ? 0.8 * v snvs 3.6 v vddotp v il ?0.00.3v v ih ?1.11.7v
12 nxp semiconductors pf0200 general product characteristics 4.3.2 current consumption table 7. current consumption summary consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, vin = 3.6 v, vddio = 1. 7 to 3.6 v, licell = 1.8 to 3.3 v, vsnvs = 3.0 v, typical external component values, unless otherwise not ed. typical values are characteri zed at vin = 3.6 v, vddio = 3. 3 v, licell = 3.0 v, vsnvs = 3.0 v an d 25 c, unless otherwise noted. mode pf0200 conditions system conditions typ. max. unit coin cell (15) , (16) , (19) vsnvs from licell all other blocks off vin = 0.0 v vsnvsvolt[2:0] = 110 no load on vsnvs 4.0 7.0 a off (15)(17) vsnvs from vin or licell wake-up from pwron active 32 k rc on all other blocks off vin uvdet no load on vsnvs, pmic able to wake-up 17 25 a sleep (18) vsnvs from vin wake-up from pwron active trimmed reference active sw3a/b pfm trimmed 16 mhz rc off 32 k rc on vrefddr disabled no load on vsnvs. ddr memories in self refresh 122 122 220 (20) 250 (21) a standby (18) vsnvs from either vin or licell sw1a/b combined in pfm sw2 in pfm sw3a/b combined in pfm swbst off trimmed 16 mhz rc enabled trimmed reference active vgen1-6 enabled vrefddr enabled no load on vsnvs. processor enabled in low power mode. all rails powered on except boost (load = 0 ma) 270 270 430 (20) 525 (21) a notes 15. at 25 c only. 16. refer to figure 4 for coin cell mode characteristics over temperature. 17. when vin is below the uvdet threshold, in the range of 1.8 v vin < 2.65 v, the quiescent current increases by 50 a, typically. 18. for pfm operation, headroom should be 300 mv or greater. 19. additional current may be drawn in the coin cell mode when r esetbmcu is pulled up to vsnvs due an internal path from resetbm cu to vin. the additional current is <30 a with a pull up resistor of 100 k . the i.mx 6 processors have an internal pull-up from the por_b pin to the vdd_snvs_in pin. if additional current in the coin cell mode is not desired for i.mx6 applications, use an external switch to d isconnect the resetbmcu path when vin is removed. pull-up resetbmcu to a rail t hat is off in the coin cell mode, for non-i.mx 6 applications. 20. from -40 to 85 c, applicable to consumer and extended industrial part numbers 21. from -40 to 105 c, applicable only to extended industrial parts
nxp semiconductors 13 pf0200 general product characteristics figure 4. coin cell mode current versus temperature 1 10 100 -40-200 20406080 temperature ( o c) pf0200 pf0200 coin cell mode current (ua)
14 nxp semiconductors pf0200 general description 5 general description the pf0200 is the power management integrated circuit (pmic) de signed primarily for use with nxp? s i.mx 6 series of application processors. 5.1 features this section summarizes the pf0200 features. ? input voltage range to pmic: 2.8 - 4.5 v ? buck regulators ? three to four channel configurable ? sw1a/b, 2.5 a; 0.3 to 1.875 v ?sw2, 1.5 a; 0.4 to 3.3 v ? sw3a/b, 2.5 a (single phase); 0.4 to 3.3 v ?sw3a, 1.25 a (independent); sw3b, 1.25 a (independent); 0.4 to 3.3 v ? dynamic voltage scaling ? modes: pwm, pfm, aps ? programmable output voltage ? programmable current limit ? programmable soft start ? programmable pwm switching frequency ? programmable ocp with fault interrupt ? boost regulator ? swbst, 5.0 to 5.15 v, 0.6 a, otg support ? modes: pfm and auto ? ocp fault interrupt ?ldos ? six user programable ldo ? vgen1, 0.80 to 1.55 v, 100 ma ? vgen2, 0.80 to 1.55 v, 250 ma ? vgen3, 1.8 to 3.3 v, 100 ma ? vgen4, 1.8 to 3.3 v, 350 ma ? vgen5, 1.8 to 3.3 v, 100 ma ? vgen6, 1.8 to 3.3 v, 200 ma ? soft start ? ldo/switch supply ? vsnvs (1.0/1.1/1 .2/1.3/1.5/1.8/3.0 v), 400 a ? ddr memory reference voltage ? vrefddr, 0.6 to 0.9 v, 10 ma ?16 mhz internal master clock ? otp(one time programmable) me mory for device configuration ? user programmable start-up sequence and timing ? battery backed memory including coin cell charger ?i 2 c interface ? user programmable standby, sleep, and off modes
nxp semiconductors 15 pf0200 general description 5.2 functional block diagram figure 5. functional block diagram 5.3 functional description 5.3.1 power generation the pf0200 pmic features three buck regulators (up to four in dependent outputs), one boost regulator, six general purpose ldos, one switch/ldo combination and a ddr voltage reference to supply voltages for the application processor and peripheral devices. the number of independent buck r egulator outputs can be conf igured from three to four, thereby providing flexibility to operate with higher current capability, or to operate as independent outputs for appl ications requiring more voltage rails with lower current deman ds. the sw3 regulator can be configured as a single phase or with two indepen dent outputs. the buck regulators provide the supply to proces sor cores and to other low-voltage circuits such as io and memory. dynamic voltage scaling is provided to allow controlled supply rail ad justments for the processor cores and/or other circuitry. depending on the system power path configuration, the six gener al purpose ldo regulators can be directly supplied from the main input supply or from the switching regulators to power peripherals, such as audio, camera, bluetooth, wi reless lan, etc. a specific v refddr voltage reference is included to provide accurate reference vo ltage for ddr memories operating with or without vtt termination. the vsnvs block behaves as an ldo, or as a bypass switch to suppl y the snvs/srtc circuitry on the i.mx processors; vsnvs may be powered from vin, or from a coin cell. 5.3.2 control logic the pf0200 pmic is fully programmable via the i 2 c interface. additional communication is prov ided by direct logic interfacing including interrupt and reset. start-up sequence of the device is selected upon the initial otp configuration explained in the start-up section, or by configuring the ?try before buy? featur e to test different power up sequences before choosing the final otp configuration. the pf0200 pmic has the interfaces for the power buttons and dedicated signaling interf acing with the processor. it also ensure s supply of critical internal logic and other circuits from the coin cell in case of brief interruptions from the main battery. a charge r for the coin cell is included as well. logic and control switching regulators sw1a/b (0.3 to 1.875v, 2.5a) linear regulators sw2 (0.4 to 3.3v, 1.5a) sw3a/b (0.4 to 3.3v) configurable 2.5a or 1.25a+1.25a boost regulator (5 to 5.15v, 600ma) usb otg supply vgen1 (0.8 to 1.55v, 100ma) vgen2 (0.8 to 1.55v, 250ma) vgen3 (1.8 to 3.3v, 100ma) vgen4 (1.8 to 3.3v, 350ma) vgen5 (1.8 to 3.3v, 100ma) vgen6 (1.8 to 3.3v, 200ma) bias & references parallel mcu interface regulator control vsnvs (1.0 to 3.0v, 400ua) rtc supply with coin cell charger pf0200 functional internal block diagram i 2 c communication & registers power generation fault detection and protection ddr voltage reference current limit short-circuit internal core voltage reference thermal otp startup configuration sequence and timing otp prototyping (try before buy) voltage phasing and frequency selection
16 nxp semiconductors pf0200 general description 5.3.2.1 interface signals pwron pwron is an input signal to the ic that generates a turn-on ev ent. it can be configured to detect a level, or an edge using the pwron_cfg bit. refer to section turn on events for more details. standby standby is an input signal to the ic. when it is asserted the part enters standby mode and when de-asserted, the part exits sta ndby mode. standby can be configured as active high or active low using the standbyinv bit. refer to the section standby mode for more details. note: when operating the pmic at vin 2.85 v and vsnvs is programmed for a 3.0 v output, a coin cell must be present to provide vsnvs, or the pmic will not reliably enter and exit the standby mode. resetbmcu resetbmcu is an open-drain, active low output configurable for two modes of operation. in its def ault mode, it is de-asserted 2 .0 to 4.0 ms after the last regulator in the start-up sequence is enabled; refer to figure 6 as an example. in this mode, the signal can be used to bring the processor out of reset, or as an indicator that al l supplies have been enabled; it is only asserted for a turn-off event. when configured for its fault mode, resetbm cu is de-asserted after the start-up sequenc e is completed only if no faults occurre d during start-up. at anytime, if a faul t occurs and persists for 1.8 ms typically, resetbmcu is asserted, low. the pf0200 is turned off if the fault persists for more than 100 ms typically. the pwron signal restarts the part, t hough if the fault persists, the sequence described above will be repeated. to enter the fault mode, set bit otp_pg_en of register otp pwrgd en to ?1?. this regi ster, 0xe8, is located on extended page 1 of the register map. to test the fault mode, the bit may be set during tbb prototyping, or the mode may be permanently chosen by programming otp fuses. sdwnb sdwnb is an open-drain, active low output t hat notifies the processor of an imminent pm ic shutdown. it is asserted low for one 32 khz clock cycle before powering down and is then de-asserted in the off state. intb intb is an open-drain, active low output. it is asserted when any fault occurs, provided that the fault interrupt is unmasked. intb is de- asserted after the fault interrupt is cl eared by software, which requires writing a ?1? to the fault interrupt bit.
nxp semiconductors 17 pf0200 functional block requirements and behaviors 6 functional block requirements and behaviors 6.1 start-up the pf0200 can be configured to start-up from either the internal otp configuration, or with a hard-coded configuration built i nto the device. the internal hard-coded configuration is enabled by connecting the vddotp pin to vcoredig through a 100 kohm resistor. the otp configuration is enabled by connecting vddotp to gnd. for np devices, selecting the ot p configuration causes the pf02 00 to not start-up. however, the pf0200 can be controlled throug h the i 2 c port for prototyping and programming. once programmed, the np device will startup with the customer programmed configuration. 6.1.1 device start-up configuration table 8 shows the default configuration which can be accessed on all de vices as described above, as we ll as the pre-programmed otp configurations. table 8. start-up configuration registers default configuration pre-programmed otp configuration all devices f0 f3 f4 f6 default i 2 c address 0x08 0x08 0x08 0x08 0x08 vsnvs_volt 3.0 v 3.0 v 3.0 v 3.0 v 3.0 v sw1ab_volt 1.375 v 1.375 v 1.375 v 1.375 v 1.375 v sw1ab_seq 1 1 2 2 2 sw2_volt 3.0 v 3.3 v 3.15 v 3.15 v 3.3 v sw2_seq 2 5 1 1 4 sw3a_volt 1.5 v 1.5 v 1.2 v 1.5 v 1.35 v sw3a_seq 3 3 4 4 3 sw3b_volt 1.5 v 1.5 v 1.2 v 1.5 v 1.35 v sw3b_seq 3 3 4 4 3 swbst_volt - 5.0 v 5.0 v 5.0 v 5.0 v swbst_seq - 13 6 6 - vrefddr_seq 3 3 4 4 3 vgen1_volt - 1.5 v 1.2 v 1.2 v 1.2 v vgen1_seq - 9 4 4 5 vgen2_volt 1.5 v 1.5 v - - 1.5 v vgen2_seq 2 10 - - - vgen3_volt - 2.5 v 1.8 v 1.8 v 2.8 v vgen3_seq - 11 3 3 5 vgen4_volt 1.8 v 1.8 v 1.8 v 1.8 v 1.8 v vgen4_seq 3 7 3 3 4 vgen5_volt 2.5 v 2.8 v 2.5 v 2.5 v 3.3 v vgen5_seq 3 12 5 5 5 vgen6_volt 2.8 v 3.3 v - - 3.0 v vgen6_seq 3 8 - - 1
18 nxp semiconductors pf0200 functional block requirements and behaviors figure 6. default start-up sequence pu config, seq_clk_speed 1.0 ms 2.0 ms 1.0 ms 1.0 ms 0.5 ms pu config, swdvs_clk 6.25 mv/ s 1.5625 mv/ s 12.5 mv/ s 12.5 mv/ s6.25 mv/ s pu config, pwron level sensitive sw1ab config sw1ab single phase, 2.0 mhz sw2 config 2.0 mhz sw3a config sw3ab single phase, 2.0 mhz sw3b config 2.0 mhz pg en resetbmcu in default mode table 8. start-up configuration (continued) registers default configuration pre-programmed otp configuration all devices f0 f3 f4 f6 uvdet licell vin vsnvs pwron sw1a/b sw2 vgen2 sw3a/b vrefddr vgen4 vgen5 vgen6 resetbmcu t d1 t d3 t d4 t d4 t r1 t r3 t r3 t r3 t d5 t r4 t r2 t d2 1v *vsnvs will start from 1.0 v if licell is valid before vin.
nxp semiconductors 19 pf0200 functional block requirements and behaviors 6.1.2 one time programmability (otp) otp allows the programming of st art-up configurations for a vari ety of applications. before perma nently programming the ic by programming fuses, a configuration may be pr ototyped by using the ?try before buy? (tbb) feature. an e rror correction code(ecc) algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed. the parameters that can be configured by otp are listed below. ? general: i 2 c slave address, pwron pin configur ation, start-up sequence and timing ? buck regulators: output voltage, single phase or independent mode configuration, switching frequency, and soft start ramp rate ? boost regulator and ldos: output voltage note: when prototyping or programming fuses, the user must ensu re that register settings are consistent with the hardware configuration. this is most important for the buck regulators, where the quantity, size, and value of the inductors depend on t he configuration (single phase or independent mode) and the switchi ng frequency. additionally, if an ldo is powered by a buck regu lator, it will be gated by the buck regulator in the start-up sequence. 6.1.2.1 start-up sequence and timing each regulator has 5-bits allocated to program its start-up time slot from a turn on event; therefore, each can be placed from position one to thirty-one in the start-up sequence. the all zeros code indica tes that a regulator is not part of the start-up sequence and will remain off. see table 10 . the delay between each position is equal; howev er, four delay options are available. see table 11 . the start-up sequence will terminate at the last programmed regulator. table 9. default start-up sequence timing parameter description min. typ. max. unit notes t d1 turn-on delay of vsnvs ? 5.0 ? ms (22) t r1 rise time of vsnvs ? 3.0 ? ms t d2 user determined delay ? 1.0 ? ms t r2 rise time of pwron ? (23) ?ms (23) t d3 turn-on delay of first regulator seq_clk_speed[1:0] = 00 ? 2.0 ? ms seq_clk_speed[1:0] = 01 ?2.5? (24) seq_clk_speed[1:0] = 10 ?4.0? seq_clk_speed[1:0] = 11 ?7.0? t r3 rise time of regulators ? 0.2 ? ms (25) t d4 delay between regulators seq_clk_speed[1:0] = 00 ? 0.5 ? ms seq_clk_speed[1:0] = 01 ?1.0? seq_clk_speed[1:0] = 10 ?2.0? seq_clk_speed[1:0] = 11 ?4.0? t r4 rise time of resetbmcu ? 0.2 ? ms t d5 turn-on delay of resetbmcu ? 2.0 ? ms notes 22. assumes licell voltage is valid before vin is applied. if lice ll is not valid before vin is applied then vsnvs turn-on delay may extend to a maximum of 24 ms. 23. depends on the external signal driving pwron. 24. default configuration. 25. rise time is a function of slew rate of regulators and nominal voltage selected.
20 nxp semiconductors pf0200 functional block requirements and behaviors 6.1.2.2 pwron pin configuration the pwron pin can be configured as either a level sensitive inpu t (pwron_cfg = 0), or as an e dge sensitive input (pwron_cfg = 1). as a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into sleep mode. as an edge sensitive input, such as when connected to a mech anical switch, a falling edge will turn on the part and if the swit ch is held low for greater than or equal to 4.0 seconds, the part will turn off or enter sleep mode. 6.1.2.3 i 2 c address configuration the i 2 c device address can be programmed from 0x08 to 0x0f. this allows flexibility to change the i 2 c address to avoid bus conflicts. address bit, i2c_slv_addr[3] in otp_i2c_addr register is hard coded to ?1? while the lower three lsbs of the i 2 c address (i2c_slv_addr[2:0]) are programmable as shown in table 13 . table 10. start-up sequence swxx_seq[4:0]/ vgenx_seq[4:0]/ vrefddr_seq[4:0] sequence 00000 off 00001 seq_clk_speed[1:0] * 1 00010 seq_clk_speed[1:0] * 2 ** ** ** ** 11111 seq_clk_speed[1:0] * 31 table 11. start-up sequence clock speed seq_clk_speed[1:0] time ( s) 00 500 01 1000 10 2000 11 4000 table 12. pwron configuration pwron_cfg mode 0 pwron pin high = on pwron pin low = off or sleep mode 1 pwron pin pulled low momentarily = on pwron pin low for 4.0 seconds = off or sleep mode table 13. i 2 c address configuration i2c_slv_addr[3] hard coded i2c_slv_addr[2:0] i 2 c device address (hex) 1 000 0x08 1 001 0x09 1 010 0x0a 1 011 0x0b
nxp semiconductors 21 pf0200 functional block requirements and behaviors 6.1.2.4 soft start ramp rate the start-up ramp rate or soft st art ramp rate can be chosen from the same options as shown in dynamic voltage scaling . 6.1.3 otp prototyping it is possible to test the desired configuration by using the ?try before buy? feature, before permanently programming fuses. t he configuration is loaded from the otp regist ers with this feature. these registers merely serve as te mporary storage for the val ues to be written to the fuses, for the values read from the fuses, or fo r the values read from the default configuration. to avoid confu sion, these registers will be referred to as the tbbo tp registers. the po rtion of the register map that concerns otp is shown in table 121 and table 122 . the contents of the tbbotp registers are initialized to zero when a valid vin is first applied. the values that are then loaded into the tbbotp registers depend on the setting of the vddotp pin and on the value of the tbb_por and fuse_por_xor bits. refer to table 14 . ? if vddotp = vcoredig (1.5 v), the values are loaded from the default configuration. ?if vddotp = 0.0 v, tbb_por = 0 and fuse_por_xor = 1, the values are loaded from the fuses. it is required to set all the fuse_porx bits to load the fuses. ?if vddotp = 0.0 v, tbb_por = 0 and fuse_por_xor = 0, the tbbotp registers remain initialized at zero. the initial value of tbb_por is always ?0?; only when vddotp = 0.0 v and tbb_por is set to ?1? ar e the values from the tbbotp registers maintained and not loaded from a different source. the contents of the tbbotp re gisters are modified by i 2 c. to communicate with i 2 c, vin must be valid and vddio, to which sda and scl are pulled up, must be powered by a 1.7 to 3.6 v supply. v in , or the coin cell voltage must be valid to maintain the contents of the registers. to power on with the contents of the tbbotp register s, the following conditions must ex ist; vin is valid, vddotp = 0 .0 v, tbb_por = 1 and there is a valid turn-on event. 6.1.4 reading otp fuses as described in the previous section, th e contents of the fuses are loaded to the t bbotp registers. when the following conditio ns are met; vin is valid, vddotp = 0.0 v, tbb_por = 0, and fuse_por_xor = 1. if ecc is enabled at the time the fuses were programmed, the error corrected values can be loaded into the tbbotp regist ers if desired. once the fuses are loaded and a turn-on event oc curs, the pmic will power on with the configuration programmed in the fuse s. contact your nxp representat ive for more details on reading the otp fuses. 6.1.5 programming otp fuses the parameters that can be programmed are shown in the tbbotp registers in the extended page 1 of the register map. the pf0200 offers ecc, the control registers for which functions are located in extended page 2 of the register map. th ere are ten banks of twenty- six fuses, each that can be programmed. 1 100 0x0c 1 101 0x0d 1 110 0x0e 1 111 0x0f table 13. i 2 c address configuration (continued) i2c_slv_addr[3] hard coded i2c_slv_addr[2:0] i 2 c device address (hex)
22 nxp semiconductors pf0200 functional block requirements and behaviors 6.2 16 mhz and 32 khz clocks there are two clocks: a trimmed 16 mhz, rc oscillator and an untrimmed 32 khz, rc oscillator. the 16 mhz oscillator is specified within -8.0/+8.0%. the 32 khz untrimmed clock is only used in the following conditions: ? vin < uvdet ? all regulators are in sleep mode ? all regulators are in pfm switching mode a 32 khz clock, derived from the 16 mhz trimmed clock, is used when accurate timing is needed under the following conditions: ? during start-up, vin > uvdet ? pwron_cfg = 1, for power button debounce timing in addition, when the 16 mhz is active in the on mode, the debounce times in table 25 are referenced to the 32 khz derived from the 16 mhz clock. the exceptions are the lowvini and pwro ni interrupts, which are referenced to the 32 khz untrimmed clock. 6.2.1 clock adjustment the 16 mhz clock and hence the switching frequency of the regulators, c an be adjusted to improve the no ise integrity of the system. by changing the factory trim values of the 16mhz cl ock, the user may add an offset as small as 3.0% of the nominal frequency. 6.3 bias and references block description 6.3.1 internal core voltage references all regulators use the main bandgap as the reference. the main bandgap is bypassed with a capacitor at vcoreref. the bandgap an d the rest of the core circuitry are supplied from vcore. the per formance of the regulators is directly dependent on the performa nce of the bandgap. no external dc loading is allowed on vcore, vcoredig, or vcoreref. vcoredig is kept powered as long as there is a valid supply and/or valid coin cell. table 16 shows the main characterist ics of the core circuitry. table 14. source of start-up sequence vddotp(v) tbb_por fuse_por_xor start-up sequence 0 0 0 none 0 0 1 otp fuses 0 1 x tbbotp registers 1.5 x x factory defined table 15. 16 mhz clock specifications consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 2.8 to 4.5 v, licell = 1.8 to 3.3 v and typical external component values. typical values are characterized at v in = 3.6 v, licell = 3.0 v, and 25 c, unless otherwise noted. symbol parameters min. typ. max. units notes v in16mhz operating voltage from vin 2.8 ? 4.5 v f 16mhz 16 mhz clock frequency 14.7 16 17.3 mhz f 2mhz 2.0 mhz clock frequency 1.84 ? 2.16 mhz (26) notes 26. 2.0 mhz clock is derived from the 16 mhz clock.
nxp semiconductors 23 pf0200 functional block requirements and behaviors 6.3.1.1 external components 6.3.2 vrefddr voltage reference vrefddr is an internal pmos half supply voltage follower capable of supplying up to 10 ma. the output voltage is at one half the input voltage. its typically used as the reference voltage for ddr memories. a filtered resistor divider is utilized to create a low- frequency pole. this divider then utilizes a voltage follower to drive the load. figure 7. vrefddr block diagram table 16. core voltages electrical specifications (28) consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 2.8 to 4.5 v, licell = 1.8 to 3.3 v, and typical external component values. typical values are characterized at v in = 3.6 v, licell = 3.0 v, and 25 c, unless otherwise noted. symbol parameters min. typ. max. units notes vcoredig (digital core supply) v coredig output voltage on mode coin cell mode and off ? ? 1.5 1.3 ? ? v (27) vcore (analog core supply) v core output voltage on mode and charging off and coin cell mode ? ? 2.775 0.0 ? ? v (27) vcoreref (bandgap / regulator reference) v coreref output voltage ? 1.2 ? v (27) v corerefacc absolute accuracy ? 0.5 ? % v corereftacc temperature drift ? 0.25 ? % notes 27. 3.0 v < v in < 4.5 v, no external loading on vcoredig, vcore, or vcorer ef. extended operation down to uvdet, but no system malfunction. 28. for information only. table 17. external components for core voltages regulator capacitor value ( f) vcoredig 1.0 vcore 1.0 vcoreref 0.22 v inrefddr vrefddr vinrefddr c half1 discharge + _ vhalf vrefddr c half2 100 nf 100 nf c refddr 1.0 uf
24 nxp semiconductors pf0200 functional block requirements and behaviors 6.3.2.1 vrefddr control register the vrefddr voltage reference is controlled by a single bit in vrefddcrtl register in table 18 . external components vrefddr specifications table 18. register vrefddcrtl - addr 0x6a name bit # r/w default description unused 3:0 ? 0x00 unused vrefddren 4 r/w 0x00 enable or disables vrefddr output voltage 0 = vrefddr disabled 1 = vrefddr enabled unused 7:5 ? 0x00 unused table 19. vrefddr ex ternal components (29) capacitor capacitance ( f) vinrefddr (30) to vhalf 0.1 vhalf to gnd 0.1 vrefddr 1.0 notes 29. use x5r or x7r capacitors. 30. vinrefddr to gnd, 1.0 f minimum capacitance is prov ided by buck regulator output. table 20. vrefddr electri cal characteristics consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, i refddr = 0.0 ma, v inrefddr = 1.5 v and typical external component values, unless otherwise note d. typical values are characterized at v in = 3.6 v, i refddr = 0.0 ma, v inrefddr = 1.5 v, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes vrefddr v inrefddr operating input voltage range 1.2 ? 1.8 v i refddr operating load current range 0.0 ? 10 ma i refddrlim current limit i refddr when v refddr is forced to v inrefddr /4 10.5 15 25 ma i refddrq quiescent current ? 8.0 ? a (31) active mode ? dc v refddr output voltage 1.2 v < v inrefddr < 1.8 v 0.0 ma < i refddr < 10 ma ? v inrefddr / 2 ?v v refddrtol output voltage tolerance (ta = -40 to 85 c) 1.2 v < v inrefddr < 1.8 v 0.6 ma i refddr 10 ma ?1.0 ? 1.0 % v refddrtol output voltage tolerance (ta = -40 to 85 c), applicable only to the extended industrial version 1.2 v < v inrefddr < 1.8 v 0.6 ma i refddr 10 ma ?1.20 ? 1.2 % v refddrlor load regulation 1.0 ma < i refddr < 10 ma 1.2 v < v inrefddr < 1.8 v ?0.40?mv/ma
nxp semiconductors 25 pf0200 functional block requirements and behaviors 6.4 power generation 6.4.1 modes of operation the operation of the pf0200 can be reduced to five stat es, or modes: on, off, slee p, standby, and coin cell. figure 8 shows the state diagram of the pf0200, along with the conditions to enter and exit from each state. active mode ? ac t onrefddr turn-on time enable to 90% of end value v inrefddr = 1.2 v, 1.8 v i refddr = 0.0 ma ? ? 100 s t offrefddr turn-off time disable to 10% of initial value v inrefddr = 1.2 v, 1.8 v i refddr = 0.0 ma ??10ms v refddrosh start-up overshoot v inrefddr = 1.2 v, 1.8 v i refddr = 0.0 ma ?1.06.0% v refddrtlr transient load response v inrefddr = 1.2 v, 1.8 v ?5.0?mv notes 31. when vrefddr is off there is a quiescent current of 1.5 a typical. table 20. vrefddr electrical characteristics (continued) consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, i refddr = 0.0 ma, v inrefddr = 1.5 v and typical external component values, unless otherwise no ted. typical values are characterized at v in = 3.6 v, i refddr = 0.0 ma, v inrefddr = 1.5 v, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
26 nxp semiconductors pf0200 functional block requirements and behaviors figure 8. state diagram to complement the state diagram in figure 8 , a description of the states is provi ded in following sections. note that v in must exceed the rising uvdet threshold to allow a power up. refer to table 27 for the uvdet thresholds. additionally, i 2 c control is not possible in the coin cell mode and the interrupt signal, intb, is only active in sleep, standby, and on states. 6.4.1.1 on mode the pf0200 enters the on mode after a turn-on event. re setbmcu is de-asserted, high, in this mode of operation. 6.4.1.2 off mode the pf0200 enters the off mode after a turn-off event. a thermal sh utdown event also forces the pf0200 into the off mode. only vcoredig and vsnvs are powered in the mode of operation. to exit the off mode, a valid turn-on event is required. resetbmcu is asserted, low, in this mode. 6.4.1.3 standby mode ? depending on standby pin configuration, stan dby is entered when the standby pin is a sserted. this is typically used for low- power mode of operation. ? when standby is de-asserted, standby mode is exited. pwron = 0 held >= 4.0 sec any swxomode bits=1 & pwronrsten = 1 (pwron_cfg=1) pwron=1 & vin > uvdet (pwron_cfg =0) or pwron= 0 < 4.0 sec & vin > uvdet (pwron_cfg=1) on pwron = 0 any swxomode bits=1 (pwron_cfg=0) or pwron=0 held >= 4.0 sec any swxomode bits=1 & pwronrsten = 1 (pwron_cfg=1) pwron=1 & vin > uvdet (pwron_cfg = 0) or pwron= 0 < 4.0 sec & vin > uvdet (pwron_cfg=1) pwron = 0 all swxomode bits= 0 (pwron_cfg = 0) or pwron = 0 held >= 4.0 sec all swxomode bits= 0 & pwronrsten = 1 (pwron_cfg = 1) off sleep coin cell vin < uvdet vin > uvdet thermal shudown standby standby asserted vin < uvdet thermal shutdown thermal shutdown standby de-asserted pwron = 0 any swxomode bits=1 (pwron_cfg=0) or pwron=0 held >= 4.0 sec any swxomode bits=1 & pwronrsten = 1 (pwron_cfg=1) pwron = 0 all swxomode bits= 0 (pwron_cfg = 0) or pwron = 0 held >= 4.0 sec all swxomode bits= 0 & pwronrsten = 1 (pwron_cfg = 1) vin < uvdet vin < uvdet
nxp semiconductors 27 pf0200 functional block requirements and behaviors a product may be designed to go into a low-power mode after perio ds of inactivity. the standby pin is provided for board level control of going in and out of such deep sleep modes (dsm). when a product is in dsm, it may be able to reduce the overall platform current by lo wering the regulator output voltage, chang ing the operating mode of the regulators or disabli ng some regulators. the configuration of the regulators in standby is pre-programmed through the i 2 c interface. note that the standby pin is programmable for active high or ac tive low polarity, and that decoding of a standby event will tak e into account the programmed input polarity as shown in table 21 . when the pf0200 is powered up first, regulator settings for the standby mode are mirrored from the regulator settings for the on mode. to change the standby pin polarity to active low, set the standb yinv bit via software first, and then change the regulator settings for standby mode as required. for simplicity, standby will gener ally be referred to as active high throughout this document. since standby pin activity is driven asynchronously to the system , a finite time is required for the internal logic to qualify and respond to the pin level changes. a programmable dela y is provided to hold off the system resp onse to a standby ev ent. this al lows the processor and peripherals some time after a standby instruction has been re ceived to terminate processes to facilitate seamless entering into standby mode. when enabled (stbydly = 01, 10, or 11) per table 22 , stbydly will delay the standby initiated response for the entire ic, until the stbydly counter expires. an allowance should be made for three additional 32 k cycles required to synchr onize the standby event. 6.4.1.4 sleep mode ? depending on pwron pin configuration, sleep mode is enter ed when pwron is de-asserted and swxomode bit is set. ? to exit sleep mode, assert the pwron pin. in the sleep mode, the regulator will use the set point as progra mmed by sw1aboff[5:0] for sw1a/b and by swxoff[6:0] for sw2 an d sw3a/b. the activated regulators will maintain settings fo r this mode and voltage until the next turn-on event. table 23 shows the control bits in sleep mode. during sleep mode, interrupts are acti ve and the intb pin will report any unmasked fault event. table 21. standby pin and polarity control standby (pin) (33) standbyinv (i 2 c bit) (34) standby control (32) 00 0 01 1 10 1 11 0 notes 32. standby = 0: system is not in standby, standby = 1: system is in standby 33. the state of the standby pin only has influence in on mode. 34. bit 6 in power control register (addr - 0x1b) table 22. standby delay - initiated response stbydly[1:0] (35) function 00 no delay 01 one 32 k period (default) 10 two 32 k periods 11 three 32 k periods notes 35. bits [5:4] in power control register (addr - 0x1b)
28 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.1.5 coin cell mode in the coin cell state, the coin cell is the only valid power source (v in = 0.0 v) to the pmic. no turn-on event is accepted in the coin cell state. transition to the off state requires that v in surpasses uvdet threshold. resetbmcu is held low in this mode. if the coin cell is depl eted, a complete system reset will o ccur. at the next appl ication of power and th e detection of a turn- on event, the system will be re-initialized with all i 2 c bits including those that reset on coin porb, are restored to their default states. 6.4.2 state machine flow summary table 24 provides a summary matrix of the pf0200 flow diagram to show the conditions needed to transition from one state to another. table 23. regulator mode control swxomode off operational mode (sleep) (36) 0off 1pfm notes 36. for sleep mode, an activated switching regulator, should use the off mode set point as programmed by sw1aboff[5:0] for sw1a/b and swxoff[6:0] for sw2 and sw3a/b. table 24. state machine flow summary state next state off coin cell sleep standby on initial state off xv in < uvdet x x pwron_cfg = 0 pwron = 1 & v in > uvdet or pwron_cfg = 1 pwron = 0 < 4.0 s & v in > undet coin cell v in > uvdet x x x x sleep thermal shutdown v in < uvdet x x pwron_cfg = 0 pwron = 1 & v in > uvdet or pwron_cfg = 1 pwron = 0 < 4.0 s & v in > undet pwron_cfg = 1 pwron = 0 4.0 s any swxomode = 1 & pwronrsten = 1 standby thermal shutdown v in < uvdet pwron_cfg = 0 pwron = 0 any swxomode = 1 or pwron_cfg = 1 pwron = 0 4.0 s any swxomode = 1 & pwronrsten = 1 x standby de-asserted pwron_cfg = 0 pwron = 0 all swxomode = 0 or pwron_cfg = 1 pwron = 0 4.0 s all swxomode = 0 & pwronrsten = 1 on thermal shutdown v in < uvdet pwron_cfg = 0 pwron = 0 any swxomode = 1 or pwron_cfg = 1 pwron = 0 4.0 s any swxomode = 1 & pwronrsten = 1 standby asserted x pwron_cfg = 0 pwron = 0 all swxomode = 0 or pwron_cfg = 1 pwron = 0 4.0 s all swxomode = 0 & pwronrsten = 1
nxp semiconductors 29 pf0200 functional block requirements and behaviors 6.4.2.1 turn on events from off and sleep modes, the pmic is powered on by a turn-on even t. the type of turn-on event depends on the configuration of pwron. pwron may be configured as an active high when pw ron_cfg = 0, or as the input of a mechanical switch when pwron_cfg = 1. v in must be greater than uvdet for the pmic to turn-on. when pwron is configured as an active high and pwron is high (pulled up to vsnvs) before v in is valid, a v in transition from 0.0 v to a voltage greater than uvde t is also a turn-on event. see the state diagram, figure 8 , and the table 24 for more details. any regulator enabled in the sleep mode will remain enabled when transitioning from sleep to on, i.e., the regulator will not be turned off and then on again to match the start-up sequence. th e following is a more detailed description of the pwron configurations: ? if pwron_cfg = 0, the pwron signal is high and v in > uvdet, the pmic will turn on; the interrupt and sense bits, pwroni and pwrons respectively, will be set. ? if pwron_cfg = 1, v in > uvdet and pwron transitions from high to low, t he pmic will turn on; the interrupt and sense bits, pwroni and pwrons respectively, will be set. the sense bit will show the real time status of the pwron pin. in this configuration, the pwron inpu t can be a mechanical switc h debounced through a programmable debouncer, pwrondbnc[1:0], to av oid a response to a very short (i.e., unintentional) key press . the interrupt is generated for both the falling and the rising edge of the pwro n pin. by default, a 30 ms interrupt debounce is applied to both falling and rising edges. the falling edge debounce timing can be extended with pwrondbnc[1:0] as defined in the table bel ow. the interrupt is cleared by software, or when cycling through the off mode. 6.4.2.2 turn off events pwron pin the pwron pin is used to power off the pf0200. the pwron pin can be configured with otp to power off the pmic under the followi ng two conditions: 1. pwron_cfg bit = 0, swxomode bit = 0 and pwron pin is low. 2. pwron_cfg bit = 1, swxomode bit = 0, pwronrsten = 1 and pwron is held low for longer than 4.0 seconds. alternatively, the system can be c onfigured to restart automaticall y by setting the restarten bit. thermal protection if the die temperature surpasses a given threshold, the thermal protection circuit will power off the pmic to avoid damage. a t urn-on event will not power on the pmic while it is in thermal protection. t he part will remain in off mode until the die temperature decrea ses below a given threshold. there are no specific interrupts re lated to this other than the warning interrupt. see power dissipation section for more detailed information. undervoltage detection when the voltage at vin drops below the undervoltage falling thre shold, uvdet, the state machine will transition to the coin ce ll mode. table 25. pwron hardware debounce bit settings bits state turn on debounce (ms) falling edge int debounce (ms) rising edge int debounce (ms) pwrondbnc[1:0] 00 0.0 31.25 31.25 01 31.25 31.25 31.25 10 125 125 31.25 11 750 750 31.25 notes 37. the sense bit, pwrons, is not debounced and follows the state of the pwron pin.
30 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.3 power tree the pf0200 pmic features four buck regulators, one boost regulato r, six general purpose ldos, one switch/ldo combination, and a ddr voltage reference to supply voltages for the application proc essor and peripheral devices. the buck regulators as well as t he boost regulator are supplied directly from the main input supply (v in ). the inputs to all of the buck regulato rs must be tied to vin, whether they are powered on or off. the six general use ldo regulators are dire ctly supplied from the main input supply or from the switchin g regulators depending on the application requirem ents. since vrefddr is intended to provide ddr me mory reference voltage, it should be supp lied by any rail supplying voltage to ddr memories; the typical applic ation recommends the use of sw3 as the input supply for vrefdd r. vsnvs is supplied by either the main in put supply or the coin cell. refer to table 26 for a summary of all power supplies provided by the pf0200. figure 9 shows a simplified power map with various recommended options to supply the different block withi n the pf0200, as well as the typical application voltage domain on the i. mx 6 application processors. note that each application power tree is dependent upo n the system?s voltage and current requirement s, therefore a proper input voltage should be selected for the regulators. the minimum operating voltage for the main v in supply is 2.8 v, for lower voltages proper operation is not guaranteed. however at initial power up, the input voltage must surpass the rising uvdet threshold before prop er operation is guaranteed. refer to the representative tables and text specifying each supply for informa tion on performance metrics and operating ranges. table 27 summarizes the uvdet thresholds. table 26. power tree summary supply output voltage (v) step size (mv) maximum load current (ma) sw1a/b 0.3 - 1.875 25 2500 sw2 0.4 - 3.3 25/50 1500 sw3a/b 0.4 - 3.3 25/50 1250 (38) swbst 5.00/5.05/5.10/5.15 50 600 vgen1 0.80 ? 1.55 50 100 vgen2 0.80 ? 1.55 50 250 vgen3 1.8 ? 3.3 100 100 vgen4 1.8 ? 3.3 100 350 vgen5 1.8 ? 3.3 100 100 vgen6 1.8 ? 3.3 100 200 vsnvs 1.0 - 3.0 na 0.4 vrefddr 0.5*sw3a_out na 10 notes 38. current rating per independent phase, when sw3a/b is set in single phase, current capability is up to 2500 ma. table 27. uvdet threshold uvdet threshold v in rising 3.1 v falling 2.65 v
nxp semiconductors 31 pf0200 functional block requirements and behaviors figure 9. pf0200 typical power map sw2 vddhigh (0.4 to 3.3 v), 1.5 a vddarm_in vddsoc_in vddhigh_in vdd_ddr_io i.mx6x mcu ldo_3p0 swbst 5.0 v, 0.6 a sw3b ddr io (0.4 to 3.3 v), 1.25 a sw3a ddr core (0.4 to 3.3 v), 1.25 a (0.3 to 1.875 v), 1.25 a sw1a core (0.3 to 1.875 v), 1.25 a usb_otg peripherals vgen1 (0.80 to 1.55 v), 100 ma vgen2 (0.80 to 1.55 v), 250 ma vgen3 (1.8 to 3.3 v), 100 ma vsnvs_in vgen4 (1.8 to 3.3 v), 350 ma vgen5 (1.8 to 3.3 v), 100 ma vgen6 (1.8 to 3.3 v), 200 ma ddr3 vrefddr 0.5*vddr, 10 ma coincell vin sw3a/b vin sw2 vin max = 3.4 v vin 2.8 - 4.5 v vin max = 3.6 v vsnvs 1.0 to 3.0 v, 400 ua mux / coin chrg vin max = 4.5 v vin sw2 vin sw2
32 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.4 buck regulators each buck regulator is capable of operat ing in pfm, aps, and pwm switching modes. 6.4.4.1 current limit each buck regulator has a programmable current limit. in an overcurrent condition, the current is limited cycle-by-cycle. if th e current limit condition persists for more than 8.0 ms, a fault interrupt is generated. 6.4.4.2 general control to improve system efficiency the buck regulators can operate in different switching modes. changing between switching modes can occur by any of the following means: i 2 c programming, exiting/entering the standby mode , exiting/entering sleep mode, and load current variation. available switching modes for buck regulators are presented in table 28 . during soft-start of the buck regulators , the controller transitions through the pfm, aps, and pwm switching modes. 3.0 ms (typical) after the output voltage reaches regulati on, the controller transitions to the selected switching mode. depending on the particular s witching mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching mod es. table 29 summarizes the buck regulator programm ability for normal and standby modes. transitioning between normal and standby modes can affect a change in switching modes as well as ou tput voltage. the rate of th e output voltage change is controlled by the dy namic voltage scaling (dvs), explained in dynamic voltage scaling . the output voltage options are the same for normal and standby modes for each regulator. table 28. switchin g mode description mode description off the regulator is switched off and the output voltage is discharged. pfm in this mode, the regulator is always in pfm mode, which is useful at light loads for optimized efficiency. pwm in this mode, the regulator is always in pwm mode operation regardless of load conditions. aps in this mode, the regulator moves automatically betw een pulse skipping mode and pwm mode depending on load conditions. table 29. regulator mode control swxmode[3:0] normal mode standby mode 0000 off off 0001 pwm off 0010 reserved reserved 0011 pfm off 0100 aps off 0101 pwm pwm 0110 pwm aps 0111 reserved reserved 1000 aps aps 1001 reserved reserved 1010 reserved reserved 1011 reserved reserved 1100 aps pfm 1101 pwm pfm 1110 reserved reserved 1111 reserved reserved
nxp semiconductors 33 pf0200 functional block requirements and behaviors when in standby mode, the regul ator outputs the voltage progra mmed in its standby voltage register and will operate in the mode selected by the swxmode[3:0] bits. upon exiting stan dby mode, the regulator will return to it s normal switching mode and its output volt age programmed in its voltage register. any regulators whose swxomode bit is set to ?1? will enter sleep mode if a pwron turn-off event occurs, and any regulator whose swxomode bit is set to ?0? will be turned off. in sleep mode, th e regulator outputs the voltage pr ogrammed in its off (sleep) v oltage register and operates in the pfm mode. the regulator will exit the sleep mode when a turn-on event occurs. any regulator whose swxomode bit is set to ?1? will remain on and change to its no rmal configuration settings when ex iting the sleep state to the o n state. any regulator whose swxomode bit is set to ?0? will be powered up with the same delay in the star t-up sequence as when powering on from off. at this point, the regulator returns to its de fault on state output voltage and switch mode settings. table 23 shows the control bits in sleep mode. when sleep mode is acti vated by the swxomode bit, the regulator will use the set point as programmed by sw1aboff[5:0] for sw1a/b and by swxoff[6:0] for sw2 and sw3a/b. dynamic voltage scaling to reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the proce ssor. 1. normal operation: the output voltage is selected by i 2 c bits sw1ab[5:0] for sw1a/b and swx[6:0] for sw2 and sw3a/b. a voltage transition initiated by i 2 c is governed by the dvs stepping rates shown in table 32 and table 33 . 2. standby mode: the output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given pr ocessor; it is selected by i 2 c bits sw1abstby[5:0] for sw1a/b and by bits swxstby[6:0] for sw2 and sw3a/b. voltage transitions initiated by a stand by event are governed by the sw1abdvsspeed[1:0] and swxdvsspeed[1:0] i 2 c bits shown in table 32 and table 33 , respectively. 3. sleep mode: the output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest st ate retention voltage of a given processor; it is selected by i 2 c bits sw1aboff[5:0] for sw1a/b a nd by bits swxoff[6:0] for sw2, and sw3a/b. voltage transitions initiated by a turn-off event are governed by the sw1abdvsspeed[1:0] and swxdvsspeed[1:0] i 2 c bits shown in table 32 and table 33 , respectively. table 30 , table 31 , table 32 , and table 33 summarize the set point control and dvs ti me stepping applied to all regulators. table 30. dvs control logic for sw1a/b standby set point selected by 0 sw1ab[5:0] 1 sw1abstby[5:0] table 31. dvs control logic for sw2 and sw3a/b standby set point selected by 0 swx[6:0] 1 swxstby[6:0] table 32. dvs speed selection for sw1a/b sw1abdvsspeed[1:0] function 00 25 mv step each 2.0 s 01 (default) 25 mv step each 4.0 s 10 25 mv step each 8.0 s 11 25 mv step each 16 s
34 nxp semiconductors pf0200 functional block requirements and behaviors the regulators have a strong sourcing capability and sinking ca pability in pwm mode, therefore the fastest rising and falling s lopes are determined by the regulator in pwm mode. however, if the regula tors are programmed in pfm or aps mode during a dvs transition, the falling slope can be influenced by the load. additionally, as the current capability in pfm mode is reduced, controlled dvs tra nsitions in pfm mode could be affected. critically timed dvs transitions are best assured with pwm mode operation. the following diagram shows the general behavior for the regulators when initiated with i 2 c programming, or standby control. during the dvs period the overcurrent cond ition on the regulator should be masked. figure 10. voltage stepping with dvs regulator phase clock the swxphase[1:0] bits select the phase of the regulator clock as shown in table 34 . by default, each regulator is initialized at 90 out of phase with respect to each other. for example, sw1a/b is set to 0 , sw2 is set to 90 and sw3a/b is set to 180 by default at power up. the swxfreq[1:0] register is used to set the desired switching frequency for each one of the buck regulators. table 36 shows the selectable options for swxfreq[1: 0]. for each frequency, all phases will be availa ble, this allows regulators operating at diff erent frequencies to have different relative switching phases. howe ver, not all combinations are practical. for example, 2.0 mhz, 90 and 4.0 mhz, 180 are the same in terms of phasing. table 35 shows the optimum phasing when using more than one switching frequency. table 33. dvs speed selection for sw2 and sw3a/b swxdvsspeed[1:0] function swx[6] = 0 or swxstby[6] = 0 function swx[6] = 1 or swxstby[6] = 1 00 25 mv step each 2.0 s 50 mv step each 4.0 s 01 (default) 25 mv step each 4.0 s 50 mv step each 8.0 s 10 25 mv step each 8.0 s 50 mv step each 16 s 11 25 mv step each 16 s 50 mv step each 32 s table 34. regulator phase clock selection swxphase[1:0] phase of clock sent to regulator (degrees) 00 0 01 90 10 180 11 270 actual output voltage example actual output voltage possible output voltage window internally controlled steps output voltage with light load initial set point voltage change request internally controlled steps output voltage requested set point initiated by i2c programming, standby control request for higher voltage request for lower voltage
nxp semiconductors 35 pf0200 functional block requirements and behaviors programmable maximum current the maximum current, iswx max , of each buck regulator is programmable. this allo ws the use of smaller inductors where lower currents are required. programmability is accompli shed by choosing the number of parallel ed power stages in each regulator. the swx_pwrstg[2:0] bits on the extended page 2 of the register map control the number of power stages. see table 37 for the programmable options. bit[0] must always be enabled to ensure th e stage with the current sensor is chosen. the default setting, swx_pwrstg[2:0] = 111, represents the highest maximum current. th e current limit for each option is also scaled by the percenta ge of power stages that are enabled. table 35. optimum phasing frequencies optimum phasing 1.0 mhz 2.0 mhz 0 180 1.0 mhz 4.0 mhz 0 180 2.0 mhz 4.0 mhz 0 180 1.0 mhz 2.0 mhz 4.0 mhz 0 90 90 table 36. regulator frequency configuration swxfreq[1:0] frequency 00 1.0 mhz 01 2.0 mhz 10 4.0 mhz 11 reserved table 37. programmable current configuration regulators control bits % of power stages enabled rated current (a) sw1ab sw1ab_pwrstg[2:0] isw1ab max 0 0 1 40% 1.0 0 1 1 80% 2.0 1 0 1 60% 1.5 1 1 1 100% 2.5 sw2 sw2_pwrstg[2:0] isw2 max 0 0 1 38% 0.55 0 1 1 75% 1.125 1 0 1 63% 0.95 1 1 1 100% 1.5 sw3a sw3a_pwrstg[2:0] isw3a max 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25
36 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.4.3 sw1a/b sw1a/b is a 2.5 a single phase regulator. the sw1alx and sw1blx pins should be connected together on the board. sw1_config[1:0] = 01 is the only configuration supported. the single phase configuration is programmed by otp by using sw1_config[1:0] bits in the register map extended page 1 , as shown in table 38 . . sw1a/b single phase in this configuration, sw1a/b is connec ted as a single phase with a single inductor. this configuration allows reduced componen t count by using only one inductor for sw1a/b. figure 11 shows the physical connection for sw1a/b in single phase. figure 11. sw1a/b single phase block diagram both sw1alx and sw1blx nodes operate at the same dvs, frequency, and phase configured by the sw1abconf register. sw3b sw3b_pwrstg[2:0] isw3b max 0 0 1 40% 0.5 0 1 1 80% 1.0 1 0 1 60% 0.75 1 1 1 100% 1.25 table 38. sw1 configuration sw1_config[1:0] description 00 reserved 01 a/b single phase 10 reserved 11 reserved table 37. programmable current configuration (continued) regulators control bits % of power stages enabled rated current (a) driver controller sw1ain sw1alx sw1fb i sense c osw1a c insw1a l sw1a i2c interface sw1a/b sw1amode sw1afault v in driver controller sw1bin sw1blx i sense c insw1b ep sw1bmode sw1bfault v in ea z1 z2 internal compensation v ref dac i2c
nxp semiconductors 37 pf0200 functional block requirements and behaviors sw1a/b setup and control registers sw1a/b output voltage is progr ammable from 0.300 to 1.875 v in steps of 25 mv. the output voltage set point is independently programmed for normal, standby, and sleep mode by setting the sw 1ab[5:0], sw1abstby[5:0], and sw1a boff[5:0] bits respectively. table 39 shows the output voltage coding for sw1a/b. note: output voltages of 0.6 v and below are not supported. table 40 provides a list of registers used to conf igure and operate sw1a/b and a detailed descr iption on each one of these register is provided in table 41 through table 45 . table 39. sw1a/b output voltage configuration set point sw1ab[5:0] sw1abstby[5:0] sw1aboff[5:0] sw1ab output (v) set point sw1ab[5:0] sw1abstby[5:0] sw1aboff[5:0] sw1ab output (v) 0 000000 0.3000 32 100000 1.1000 1 000001 0.3250 33 100001 1.1250 2 000010 0.3500 34 100010 1.1500 3 000011 0.3750 35 100011 1.1750 4 000100 0.4000 36 100100 1.2000 5 000101 0.4250 37 100101 1.2250 6 000110 0.4500 38 100110 1.2500 7 000111 0.4750 39 100111 1.2750 8 001000 0.5000 40 101000 1.3000 9 001001 0.5250 41 101001 1.3250 10 001010 0.5500 42 101010 1.3500 11 001011 0.5750 43 101011 1.3750 12 001100 0.6000 44 101100 1.4000 13 001101 0.6250 45 101101 1.4250 14 001110 0.6500 46 101110 1.4500 15 001111 0.6750 47 101111 1.4750 16 010000 0.7000 48 110000 1.5000 17 010001 0.7250 49 110001 1.5250 18 010010 0.7500 50 110010 1.5500 19 010011 0.7750 51 110011 1.5750 20 010100 0.8000 52 110100 1.6000 21 010101 0.8250 53 110101 1.6250 22 010110 0.8500 54 110110 1.6500 23 010111 0.8750 55 110111 1.6750 24 011000 0.9000 56 111000 1.7000 25 011001 0.9250 57 111001 1.7250 26 011010 0.9500 58 111010 1.7500 27 011011 0.9750 59 111011 1.7750 28 011100 1.0000 60 111100 1.8000 29 011101 1.0250 61 111101 1.8250 30 011110 1.0500 62 111110 1.8500 31 011111 1.0750 63 111111 1.8750
38 nxp semiconductors pf0200 functional block requirements and behaviors table 40. sw1a/b register summary register address output sw1abvolt 0x20 sw1ab output voltage set point in normal operation sw1abstby 0x21 sw1ab output voltage set point on standby sw1aboff 0x22 sw1ab output voltage set point on sleep sw1abmode 0x23 sw1ab switching mode selector register sw1abconf 0x24 sw1ab dvs, phase, frequency and ilim configuration table 41. register sw1abvolt - addr 0x20 name bit # r/w default description sw1ab 5:0 r/w 0x00 sets the sw1ab output voltage during normal operation mode. see table 39 for all possible configurations. unused 7:6 ? 0x00 unused table 42. register sw1abstby - addr 0x21 name bit # r/w default description sw1abstby 5:0 r/w 0x00 sets the sw1ab output voltage during standby mode. see table 39 for all possible configurations. unused 7:6 ? 0x00 unused table 43. register sw1aboff - addr 0x22 name bit # r/w default description sw1aboff 5:0 r/w 0x00 sets the sw1ab output voltage during sleep mode. see table 39 for all possible configurations. unused 7:6 ? 0x00 unused table 44. register sw1abmode - addr 0x23 name bit # r/w default description sw1abmode 3:0 r/w 0x80 sets the sw1ab switching operation mode. see table 29 for all possible configurations. unused 4 ? 0x00 unused sw1abomode 5 r/w 0x00 set status of sw1ab when in sleep mode 0 = off 1 = pfm unused 7:6 ? 0x00 unused
nxp semiconductors 39 pf0200 functional block requirements and behaviors sw1a/b external components table 45. register sw1abconf - addr 0x24 name bit # r/w default description sw1abilim 0 r/w 0x00 sw1ab current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw1abfreq 3:2 r/w 0x00 sw1a/b switching frequency selector see table 36 . sw1abphase 5:4 r/w 0x00 sw1a/b phase clock selection see table 34 . sw1abdvsspeed 7:6 r/w 0x00 sw1a/b dvs speed selection see table 32 . table 46. sw1a/b external component recommendations components description mode a/b single phase c insw1a (39) sw1a input capacitor 4.7 f c in1ahf (39) sw1a decoupling input capacitor 0.1 f c insw1b (39) sw1b input capacitor 4.7 f c in1bhf (39) sw1b decoupling input capacitor 0.1 f c osw1ab (39) sw1a/b output capacitor 4 x 22 f l sw1a sw1a/b inductor 1.0 h dcr = 12 m i sat = 4.5 a notes 39. use x5r or x7r capacitors.
40 nxp semiconductors pf0200 functional block requirements and behaviors sw1a/b specifications table 47. sw1a/b electrical characteristics all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin sw1x = 3.6 v, v sw1ab = 1.2 v, i sw1ab = 100 ma, sw1ab_pwrstg[2:0] = [111], ty pical external component values, f sw1ab = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw1x = 3.6 v, v sw1av = 1.2 v, i sw1ab = 100 ma, sw1ab_pwrstg[2:0 ] = [111], and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes sw1a/b (single phase) vin sw1a vin sw1b operating input voltage 2.8 ? 4.5 v v sw1ab nominal output voltage ? table 39 ?v v sw1abacc output voltage accuracy ? pwm, aps, 2.8 v < v in < 4.5 v, 0 < i sw1ab < 2.5 a 0.625 v v sw1ab 1.450 v 1.475 v v sw1ab 1.875 v ? pfm, steady state, 2.8 v < v in < 4.5 v, 0 < i sw1ab < 150 ma 0.625 v < v sw1ab < 0.675 v 0.7 v < v sw1ab < 0.85 v 0.875 v < v sw1ab < 1.875 v -25 -3.0% -65 -45 -3.0% - - ? ? ? 25 3.0% 65 45 3.0% mv % (40) i sw1ab rated output load current, 2.8 v < v in < 4.5 v, 0.625 v < v sw1ab < 1.875 v ? ? 2500 ma (41) i sw1ablim current limiter peak current detection ? sw1a/b single phase (current through inductor) sw1abilim = 0 sw1abilim = 1 4.5 3.3 6.5 4.9 8.5 6.4 a (41) v sw1abosh start-up overshoot i sw1ab = 0.0 ma dvs clk = 25 mv/4 s, v in = vin sw1x = 4.5 v, v sw1ab = 1.875 v ??66mv ton sw1ab turn-on time enable to 90% of end value i sw1ab = 0.0 ma dvs clk = 25 mv/4 s, v in = vin sw1x = 4.5 v, v sw1ab = 1.875 v ? ? 500 s f sw1ab switching frequency sw1abfreq[1:0] = 00 sw1abfreq[1:0] = 01 sw1abfreq[1:0] = 10 ? ? ? 1.0 2.0 4.0 ? ? ? mhz sw1ab efficiency (single phase) ?v in = 3.6 v, f sw1ab = 2.0 mhz, l sw1ab = 1.0 h pfm, 0.9 v, 1.0 ma pfm, 1.2 v, 50 ma aps, pwm, 1.2 v, 500 ma aps, pwm, 1.2 v, 750 ma aps, pwm, 1.2 v, 1250 ma aps, pwm, 1.2 v, 2500 ma ? ? ? ? ? ? 82 84 86 87 82 71 ? ? ? ? ? ? % v sw1ab output ripple ? 10 ? mv v sw1ablir line regulation (aps, pwm) ? ? 20 mv v sw1ablor dc load regulation (aps, pwm) ? ? 20 mv v sw1ablotr transient load regulation ? transient load = 0 to 1.25 a, di/dt = 100 ma/ s overshoot undershoot ? ? ? ? 50 50 mv
nxp semiconductors 41 pf0200 functional block requirements and behaviors figure 12. sw1ab efficiency waveforms sw1a/b (single phase) (continued) i sw1abq quiescent current pfm mode aps mode ? ? 18 235 ? ? a r onsw1ap sw1a p-mosfet r dson vin sw1a = 3.3 v ? 215 245 m r onsw1an sw1a n-mosfet r dson vin sw1a = 3.3 v ? 258 326 m i sw1apq sw1a p-mosfet leakage current vin sw1a = 4.5 v ??7.5a i sw1anq sw1a n-mosfet leakage current vin sw1a = 4.5 v ??2.5a r onsw1bp sw1b p-mosfet r dson vin sw1b = 3.3 v ? 215 245 m r onsw1bn sw1b n-mosfet r dson vin sw1b = 3.3 v ? 258 326 m i sw1bpq sw1b p-mosfet leakage current vin sw1b = 4.5 v ??7.5a i sw1bnq sw1b n-mosfet leakage current vin sw1b = 4.5 v ??2.5a r sw1abdis discharge resistance ? 600 ? notes 40. accuracy specification is incl usive of load and line regulation. 41. current rating of sw1ab supports the power virus mode of operation of the i.mx6x processor. table 47. sw1a/b electrical characteristics (continued) all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin sw1x = 3.6 v, v sw1ab = 1.2 v, i sw1ab = 100 ma, sw1ab_pwrstg[2:0] = [111], typical external component values, f sw1ab = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw1x = 3.6 v, v sw1av = 1.2 v, i sw1ab = 100 ma, sw1ab_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 e f f i c i e n c y ( % ) load current (ma) pfm - vout = 1.2v aps - vout = 1.2v pwm - vout = 1.2v efficiency (%) sw1ab single phase
42 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.4.4 sw2 sw2 is a single phase, 1.5 a rated buck regulator. table 28 describes the modes, and table 29 show the options for the swxmode[3:0] bits. figure 13 shows the block diagram and the external component connections for sw2 regulator. figure 13. sw2 block diagram sw2 setup and control registers sw2 output voltage is progr ammable from 0.400 to 3.300 v; however, bit sw2[6] in register sw2volt is read-only during normal operation. its value is determined by the default configurat ion, or may be changed by using the otp registers. therefore, once sw2[6] is set to ?0?, the output will be limited to th e lower output voltages from 0.400 to 1.975 v with 25 mv increments, as determined by bits sw2[5:0]. likewise, onc e bit sw2[6] is set to ?1?, the out put voltage will be limited to the higher output voltage range from 0 .800 to 3.300 v with 50 mv increments, as determi ned by bits sw2[5:0]. in order to optimize the performance of the regulator, it is recommended that only voltages from 2.000 to 3.300 v be used in the high range, and the lower range be used for voltages from 0.400 to 1.975 v. the output voltage set point is independently programmed for normal, standby, and sleep mode by setting the sw2[5:0], sw2stby[5 :0] and sw2off[5:0] bits, respectively. however, the initial state of bit sw2[6] will be co pied into bits sw2s tby[6], and sw2off[6] bits. therefore, the out put voltage range will remain the same in all three operating modes. table 48 shows the output voltage coding valid for sw2. note: output voltages of 0.6 v and below are not supported. table 48. sw2 output voltage configuration low output voltage range (42) high output voltage range set point sw2[6:0] sw2stby[6:0] sw2off[6:0] sw2 output set point sw2[6:0] sw2stby[6:0] sw2off[6:0] sw2 output 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 driver controller ea z1 z2 internal compensation sw2in sw2lx sw2fb i sense c osw2 c insw2 l sw2 i2c interface ep sw2 sw2mode sw2fault v ref dac i2c vin
nxp semiconductors 43 pf0200 functional block requirements and behaviors 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 table 48. sw2 output voltage configuration (continued) low output voltage range (42) high output voltage range set point sw2[6:0] sw2stby[6:0] sw2off[6:0] sw2 output set point sw2[6:0] sw2stby[6:0] sw2off[6:0] sw2 output
44 nxp semiconductors pf0200 functional block requirements and behaviors setup and control of sw2 is done through i 2 c registers listed in table 49 , and a detailed description of each one of the registers is provided in tables 50 to table 54 . 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 reserved 52 0110100 1.7000 116 1110100 reserved 53 0110101 1.7250 117 1110101 reserved 54 0110110 1.7500 118 1110110 reserved 55 0110111 1.7750 119 1110111 reserved 56 0111000 1.8000 120 1111000 reserved 57 0111001 1.8250 121 1111001 reserved 58 0111010 1.8500 122 1111010 reserved 59 0111011 1.8750 123 1111011 reserved 60 0111100 1.9000 124 1111100 reserved 61 0111101 1.9250 125 1111101 reserved 62 0111110 1.9500 126 1111110 reserved 63 0111111 1.9750 127 1111111 reserved notes 42. for voltages less than 2.0 v, only use set points 0 to 63 table 49. sw2 register summary register address description sw2volt 0x35 output voltage set point on normal operation sw2stby 0x36 output voltage set point on standby sw2off 0x37 output voltage set point on sleep sw2mode 0x38 switching mode selector register sw2conf 0x39 dvs, phase, frequency, and ilim configuration table 50. register sw2volt - addr 0x35 name bit # r/w default description sw2 5:0 r/w 0x00 sets the sw2 output voltage during normal operation mode. see table 48 for all possible configurations. sw2 6 r 0x00 sets the operating output voltage range for sw2. set during otp or tbb configuration only. see table 48 for all possible configurations. unused 7 ? 0x00 unused table 48. sw2 output voltage configuration (continued) low output voltage range (42) high output voltage range set point sw2[6:0] sw2stby[6:0] sw2off[6:0] sw2 output set point sw2[6:0] sw2stby[6:0] sw2off[6:0] sw2 output
nxp semiconductors 45 pf0200 functional block requirements and behaviors table 51. register sw2stby - addr 0x36 name bit # r/w default description sw2stby 5:0 r/w 0x00 sets the sw2 output voltage during standby mode. see table 48 for all possible configurations. sw2stby 6 r 0x00 sets the operating output voltage range for sw2 on standby mode. this bit inherits the value configured on bit sw2[6] during otp or tbb configuration. see table 48 for all possible configurations. unused 7 ? 0x00 unused table 52. register sw2off - addr 0x37 name bit # r/w default description sw2off 5:0 r/w 0x00 sets the sw2 output voltage during sleep mode. see table 48 for all possible configurations. sw2off 6 r 0x00 sets the operating output voltage range for sw2 on sleep mode. this bit inherits the value configured on bit sw2[6] during otp or tbb configuration. see table 48 for all possible configurations. unused 7 ? 0x00 unused table 53. register sw2mode - addr 0x38 name bit # r/w default description sw2mode 3:0 r/w 0x80 sets the sw2 switching operation mode. see table 28 for all possible configurations. unused 4 ? 0x00 unused sw2omode 5 r/w 0x00 set status of sw2 when in sleep mode 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 54. register sw2conf - addr 0x39 name bit # r/w default description sw2ilim 0 r/w 0x00 sw2 current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw2freq 3:2 r/w 0x00 sw2 switching frequency selector. see table 36 . sw2phase 5:4 r/w 0x00 sw2 phase clock selection. see table 34 . sw2dvsspeed 7:6 r/w 0x00 sw2 dvs speed selection. see table 33 .
46 nxp semiconductors pf0200 functional block requirements and behaviors sw2 external components sw2 specifications table 55. sw2 external component recommendations components description values c insw2 (43) sw2 input capacitor 4.7 f c in2hf (43) sw2 decoupling input capacitor 0.1 f c osw2 (43) sw2 output capacitor 2 x 22 f l sw2 sw2 inductor 1.0 h dcr = 50 m i sat = 2.65 a notes 43. use x5r or x7r capacitors. table 56. sw2 electrical characteristics all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], typical external component values, f sw2 = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes switch mode supply sw2 vin sw2 operating input voltage 2.8 ? 4.5 v (44) v sw2 nominal output voltage ? table 48 ?v v sw2acc output voltage accuracy ? pwm, aps, 2.8 v < v in < 4.5 v, 0 < i sw2 < 1.5 a 0.625 v < v sw2 < 0.85 v 0.875 v < v sw2 < 1.975 v 2.0 v < v sw2 < 3.3 v ? pfm, 2.8 v < v in < 4.5 v, 0 < i sw2 50 ma 0.625 v < v sw2 < 0.675 v 0.7 v < v sw2 < 0.85 v 0.875 v < v sw2 < 1.975 v 2.0 v < v sw2 < 3.3 v -25 -3.0% -6.0% -65 -45 -3.0% -3.0% ? ? ? ? ? ? ? 25 3.0% 6.0% 65 45 3.0% 3.0% mv % (45) i sw2 rated output load current 2.8 v < v in < 4.5 v, 0.625 v < v sw2 < 3.3 v ? ? 1500 ma (46) i sw2lim current limiter peak current detection ? current through inductor sw2ilim = 0 sw2ilim = 1 2.1 1.57 3.0 2.25 3.9 2.93 a v sw2osh start-up overshoot i sw2 = 0.0 ma dvs clk = 25 mv/4 s, v in = vin sw2 = 4.5 v ??66mv ton sw2 turn-on time enable to 90% of end value i sw2 = 0.0 ma dvs clk = 50 mv/8 s, v in = vin sw2 = 4.5 v ? ? 550 s f sw2 switching frequency sw2freq[1:0] = 00 sw2freq[1:0] = 01 sw2freq[1:0] = 10 ? ? ? 1.0 2.0 4.0 ? ? ? mhz
nxp semiconductors 47 pf0200 functional block requirements and behaviors sw2 efficiency ?v in = 3.6 v, f sw2 = 2.0 mhz, l sw2 = 1.0 h pfm, 3.15 v, 1.0 ma pfm, 3.15 v, 50 ma aps, pwm, 3.15 v, 400 ma aps, pwm, 3.15 v, 600 ma aps, pwm, 3.15 v, 1000 ma aps, pwm, 3.15 v, 1500 ma ? ? ? ? ? ? 94 95 96 94 92 89 ? ? ? ? ? ? % switch mode supply sw2 (continued) v sw2 output ripple ? 10 ? mv v sw2lir line regulation (aps, pwm) ? ? 20 mv v sw2lor dc load regulation (aps, pwm) ? ? 20 mv v sw2lotr transient load regulation ? transient load = 0.0 ma to 1.0 a, di/dt = 100 ma/ s overshoot undershoot ? ? ? ? 50 50 mv i sw2q quiescent current pfm mode aps mode (low output voltage settings) aps mode (high output voltage settings) ? ? ? 23 145 305 ? ? ? a r onsw2p sw2 p-mosfet r dson at v in = vin sw2 = 3.3 v ? 190 209 m r onsw2n sw2 n-mosfet r dson at v in = vin sw2 = 3.3 v ? 212 255 m i sw2pq sw2 p-mosfet leakage current v in = vin sw2 = 4.5 v ??12a i sw2nq sw2 n-mosfet leakage current v in = vin sw2 = 4.5 v ??4.0a r sw2dis discharge resistance ? 600 ? notes 44. when output is set to > 2.6 v the output will follow the input down when v in gets near 2.8 v. 45. accuracy specification is incl usive of load and line regulation. 46. the higher output voltages available depend on the voltage drop in the conduction path as giv en by the following equation: (vin sw2 - v sw2 ) = i sw2 * (dcr of inductor +r onsw2p + pcb trace resistance). table 56. sw2 electrical characteristics (continued) all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], ty pical external component values, f sw2 = 2.0 mhz, unless otherwise noted. typical values are characterized at v in = vin sw2 = 3.6 v, v sw2 = 3.15 v, i sw2 = 100 ma, sw2_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
48 nxp semiconductors pf0200 functional block requirements and behaviors figure 14. sw2 efficiency waveforms 6.4.4.5 sw3a/b sw3a/b are 1.25 to 2.5 a rated buck regulators, depending on the configuration. table 28 describes the available switching modes and table 29 show the actual configuration opt ions for the sw3xmode[3:0] bits. sw3a/b can be configured in various phasing schemes, dependi ng on the desired cost/perfo rmance trade-offs. the following configurations are available: ? a single phase ? independent regulators the desired configuration is programmed in otp by using the sw3_config[1:0] bits. table 57 shows the options for the sw3cfg[1:0] bits. sw3a/b single phase in this configuration, sw3alx an d sw3blx are connected in single phase with a single inductor a shown in figure 15 . this configuration reduces cost and component count. feedback is taken from the sw3afb pin and the sw3b fb pin must be left open. although control is from sw3a, registers of both regulators , sw3a and sw3b, must be identically set. table 57. sw3 configuration sw3_config[1:0] description 00 a/b single phase 01 a/b single phase 10 reserved 11 a/b independent 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 e f f i c i e n c y ( % ) load current (ma) pfm - vout = 3.15v aps - vout = 3.15v pwm - vout = 3.15v efficiency (%)
nxp semiconductors 49 pf0200 functional block requirements and behaviors figure 15. sw3a/b single phase block diagram driver controller sw3ain sw3alx sw3afb i sense c osw3a c insw3a l sw3a i2c interface sw3 sw3amode sw3afault vin driver controller sw3bin sw3blx i sense c insw3b ep sw3bmode sw3bfault vin ea z1 z2 internal compensation v ref dac i2c ea z1 z2 internal compensation v ref dac i2c sw3bfb
50 nxp semiconductors pf0200 functional block requirements and behaviors sw3a - sw3b independent outputs sw3a and sw3b can be configured as independent outputs as shown in figure 16 , providing flexibility for applications requiring more voltage rails with less current capability. each output is configured and controlled independently by its respective i 2 c registers as shown in table 59 . figure 16. sw3a/b independent output block diagram sw3a/b setup and control registers sw3a/b output voltage is progr ammable from 0.400 to 3.300 v; however, bit sw3x[6] in register sw3xvolt is read-only during normal operation. its value is determined by the defa ult configuration, or may be changed by using the otp registers. therefore, once sw3x[6] is set to ?0?, the output will be limited to th e lower output voltages from 0.40 to 1.975 v with 25 mv increments, as determined by bits sw3x[5:0]. likewise, once bit sw3x[6] is set to "1", the output voltage will be limited to the higher output voltage range from 0.800 to 3.300 v with 50 mv increments, as determined by bits sw3x[5:0]. in order to optimize the performance of the regulator, it is recommended that only voltages from 2.00 to 3.300 v be used in the high range and that that the lower range be us ed for voltages from 0.400 to 1.975 v. the output voltage set point is independently programmed for normal, standby, and sleep mode by setting the sw3x[5:0], sw3xstby[5:0], and sw3xoff[5:0] bits respectively; however, the initial state of the sw3x[6] bit will be copied into the sw3xst by[6] and sw3xoff[6] bits. therefore, t he output voltage range will remain t he same on all three operating modes. table 58 shows the output voltage coding valid for sw3x. note: output voltages of 0.6 v and below are not supported. driver controller ea z1 z2 internal compensation sw3ain sw3alx sw3afb i sense c osw3a c insw3a l sw3a i2c interface sw3a sw3amode sw3afault v ref dac i2c vin driver controller ea z1 z2 internal compensation sw3bin sw3blx sw3bfb i sense c osw3b c insw3b l sw3b ep sw3b sw3bmode sw3bfault v ref dac i2c vin
nxp semiconductors 51 pf0200 functional block requirements and behaviors table 58. sw3a/b output voltage configuration low output voltage range (47) high output voltage range set point sw3x[6:0] sw3xstby[6:0] sw3xoff[6:0] sw3x output set point sw3x[6:0] sw3xstby[6:0] sw3xoff[6:0] sw3xoutput 0 0000000 0.4000 64 1000000 0.8000 1 0000001 0.4250 65 1000001 0.8500 2 0000010 0.4500 66 1000010 0.9000 3 0000011 0.4750 67 1000011 0.9500 4 0000100 0.5000 68 1000100 1.0000 5 0000101 0.5250 69 1000101 1.0500 6 0000110 0.5500 70 1000110 1.1000 7 0000111 0.5750 71 1000111 1.1500 8 0001000 0.6000 72 1001000 1.2000 9 0001001 0.6250 73 1001001 1.2500 10 0001010 0.6500 74 1001010 1.3000 11 0001011 0.6750 75 1001011 1.3500 12 0001100 0.7000 76 1001100 1.4000 13 0001101 0.7250 77 1001101 1.4500 14 0001110 0.7500 78 1001110 1.5000 15 0001111 0.7750 79 1001111 1.5500 16 0010000 0.8000 80 1010000 1.6000 17 0010001 0.8250 81 1010001 1.6500 18 0010010 0.8500 82 1010010 1.7000 19 0010011 0.8750 83 1010011 1.7500 20 0010100 0.9000 84 1010100 1.8000 21 0010101 0.9250 85 1010101 1.8500 22 0010110 0.9500 86 1010110 1.9000 23 0010111 0.9750 87 1010111 1.9500 24 0011000 1.0000 88 1011000 2.0000 25 0011001 1.0250 89 1011001 2.0500 26 0011010 1.0500 90 1011010 2.1000 27 0011011 1.0750 91 1011011 2.1500 28 0011100 1.1000 92 1011100 2.2000 29 0011101 1.1250 93 1011101 2.2500 30 0011110 1.1500 94 1011110 2.3000 31 0011111 1.1750 95 1011111 2.3500 32 0100000 1.2000 96 1100000 2.4000 33 0100001 1.2250 97 1100001 2.4500 34 0100010 1.2500 98 1100010 2.5000 35 0100011 1.2750 99 1100011 2.5500
52 nxp semiconductors pf0200 functional block requirements and behaviors 36 0100100 1.3000 100 1100100 2.6000 37 0100101 1.3250 101 1100101 2.6500 38 0100110 1.3500 102 1100110 2.7000 39 0100111 1.3750 103 1100111 2.7500 40 0101000 1.4000 104 1101000 2.8000 41 0101001 1.4250 105 1101001 2.8500 42 0101010 1.4500 106 1101010 2.9000 43 0101011 1.4750 107 1101011 2.9500 44 0101100 1.5000 108 1101100 3.0000 45 0101101 1.5250 109 1101101 3.0500 46 0101110 1.5500 110 1101110 3.1000 47 0101111 1.5750 111 1101111 3.1500 48 0110000 1.6000 112 1110000 3.2000 49 0110001 1.6250 113 1110001 3.2500 50 0110010 1.6500 114 1110010 3.3000 51 0110011 1.6750 115 1110011 reserved 52 0110100 1.7000 116 1110100 reserved 53 0110101 1.7250 117 1110101 reserved 54 0110110 1.7500 118 1110110 reserved 55 0110111 1.7750 119 1110111 reserved 56 0111000 1.8000 120 1111000 reserved 57 0111001 1.8250 121 1111001 reserved 58 0111010 1.8500 122 1111010 reserved 59 0111011 1.8750 123 1111011 reserved 60 0111100 1.9000 124 1111100 reserved 61 0111101 1.9250 125 1111101 reserved 62 0111110 1.9500 126 1111110 reserved 63 0111111 1.9750 127 1111111 reserved notes 47. for voltages less than 2.0 v, only use set points 0 to 63. table 58. sw3a/b output voltage configuration (continued) low output voltage range (47) high output voltage range set point sw3x[6:0] sw3xstby[6:0] sw3xoff[6:0] sw3x output set point sw3x[6:0] sw3xstby[6:0] sw3xoff[6:0] sw3xoutput
nxp semiconductors 53 pf0200 functional block requirements and behaviors table 59 provides a list of registers used to c onfigure and operate sw3a/b. a detailed description on each of these register is provide d on tables 60 through table 69 . table 59. sw3ab register summary register address output sw3avolt 0x3c sw3a output voltage set point on normal operation sw3astby 0x3d sw3a output voltage set point on standby sw3aoff 0x3e sw3a output voltage set point on sleep sw3amode 0x3f sw3a switching mode selector register sw3aconf 0x40 sw3a dvs, phase, frequency and ilim configuration sw3bvolt 0x43 sw3b output voltage set point on normal operation sw3bstby 0x44 sw3b output voltage set point on standby sw3boff 0x45 sw3b output voltage set point on sleep sw3bmode 0x46 sw3b switching mode selector register sw3bconf 0x47 sw3b dvs, phase, frequency and ilim configuration table 60. register sw3avolt - addr 0x3c name bit # r/w default description sw3a 5:0 r/w 0x00 sets the sw3a output voltage (independent) or sw3a/b output voltage (single phase), during normal operation mode. see table 58 for all possible configurations. sw3a 6 r 0x00 sets the operating output voltage range for sw3a (independent) or sw3a/b (single phase). set during otp or tbb configuration only. see table 58 for all possible configurations. unused 7 ? 0x00 unused table 61. register sw3astby - addr 0x3d name bit # r/w default description sw3astby 5:0 r/w 0x00 sets the sw3a output voltage (independent) or sw3a/b output voltage (single phase), during standby mode. see table 58 for all possible configurations. sw3astby 6 r 0x00 sets the operating output voltage range for sw3a (independent) or sw3a/b (single phase) on standby mode. this bit inherits the value configured on bit sw3a[6] during otp or tbb configuration. see table 58 for all possible configurations. unused 7 ? 0x00 unused
54 nxp semiconductors pf0200 functional block requirements and behaviors table 62. register sw3aoff - addr 0x3e name bit # r/w default description sw3aoff 5:0 r/w 0x00 sets the sw3a output voltage (independent) or sw3a/b output voltage (single phase), during sleep mode. see table 58 for all possible configurations. sw3aoff 6 r 0x00 sets the operating output voltage range for sw3a (independent) or sw3a/b (single phase) on sleep mode. this bit inherits the value configured on bit sw3a[6] during otp or tbb configuration. see table 58 for all possible configurations. unused 7 ? 0x00 unused table 63. register sw3amode - addr 0x3f name bit # r/w default description sw3amode 3:0 r/w 0x80 sets the sw3a (independent) or sw3a/b (single phase) switching operation mode. see table 28 for all possible configurations. unused 4 ? 0x00 unused sw3aomode 5 r/w 0x00 set status of sw3a (independent) or sw3a/b (single phase) when in sleep mode. 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 64. register sw3aconf - addr 0x40 name bit # r/w default description sw3ailim 0 r/w 0x00 sw3a current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw3afreq 3:2 r/w 0x00 sw3a switching frequency selector. see table 36 . sw3aphase 5:4 r/w 0x00 sw3a phase clock selection. see table 34 . sw3advsspeed 7:6 r/w 0x00 sw3a dvs speed selection. see table 33 . table 65. register sw3bvolt - addr 0x43 name bit # r/w default description sw3b 5:0 r/w 0x00 sets the sw3b output voltage (independent) during normal operation mode. see table 58 for all possible configurations. sw3b 6 r 0x00 sets the operating output voltage range for sw3b (independent). set during otp or tbb configuration only. see table 58 for all possible configurations. unused 7 ? 0x00 unused
nxp semiconductors 55 pf0200 functional block requirements and behaviors table 66. register sw3bstby - addr 0x44 name bit # r/w default description sw3bstby 5:0 r/w 0x00 sets the sw3b output voltage (independent) during standby mode. see table 58 for all possible configurations. sw3bstby 6 r 0x00 sets the operating output voltage range for sw3b (independent) on standby mode. this bit inherits the value configured on bit sw3b[6] during otp or tbb configuration. see table 58 for all possible configurations. unused 7 ? 0x00 unused table 67. register sw3boff - addr 0x45 name bit # r/w default description sw3boff 5:0 r/w 0x00 sets the sw3b output voltage (independent) during sleep mode. see table 58 for all possible configurations. sw3boff 6 r 0x00 sets the operating output voltage range for sw3b (independent) on sleep mode. this bit inherits the value configured on bit sw3b[6] during otp or tbb configuration. see table 58 for all possible configurations. unused 7 ? 0x00 unused table 68. register sw3bmode - addr 0x46 name bit # r/w default description sw3bmode 3:0 r/w 0x80 sets the sw3b (independent) switching operation mode. see table 28 for all possible configurations. unused 4 ? 0x00 unused sw3bomode 5 r/w 0x00 set status of sw3b (independent) when in sleep mode. 0 = off 1 = pfm unused 7:6 ? 0x00 unused table 69. register sw3bconf - addr 0x47 name bit # r/w default description sw3bilim 0 r/w 0x00 sw3b current limit level selection 0 = high level current limit 1 = low level current limit unused 1 r/w 0x00 unused sw3bfreq 3:2 r/w 0x00 sw3b switching frequency selector. see table 36 . sw3bphase 5:4 r/w 0x00 sw3b phase clock selection. see table 34 . sw3bdvsspeed 7:6 r/w 0x00 sw3b dvs speed selection. see table 33 .
56 nxp semiconductors pf0200 functional block requirements and behaviors sw3a/b external components sw3a/b specifications table 70. sw3a/b external component requirements mode components description sw3a/b single phase sw3a independent sw3b independent c insw3a (48) sw3a input capacitor 4.7 f4.7 f c in3ahf (48) sw3a decoupling input capacitor 0.1 f0.1 f c insw3b (48) sw3b input capacitor 4.7 f4.7 f c in3bhf (48) sw3b decoupling input capacitor 0.1 f0.1 f c osw3a (48) sw3a output capacitor 4 x 22 f2 x 22 f c osw3b (48) sw3b output capacitor ? 2 x 22 f l sw3a sw3a inductor 1.0 h dcr = 50 m i sat = 3.9 a 1.0 h dcr = 60 m i sat = 3.0 a l sw3b sw3b inductor ? 1.0 h dcr = 60 m i sat = 3.0 a notes 48. use x5r or x7r capacitors. table 71. sw3a/b electrical characteristics all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], typical external component values, f sw3x = 2.0 mhz, single phase and independent mode unless, otherwise noted. typical values are characterized at v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. symbol p arameter min. typ. max. unit notes switch mode supply sw3a/b vin sw3x operating input voltage (49) 2.8 ? 4.5 v v sw3x nominal output voltage - table 58 -v v sw3xacc output voltage accuracy ? pwm, aps 2.8 v < v in < 4.5 v, 0 < i sw3x < isw3x max 0.625 v < v sw3x < 0.85 v 0.875 v < v sw3x < 1.975 v 2.0 v < v sw3x < 3.3 v ? pfm , steady state (2.8 v < v in < 4.5 v, 0 < i sw3x < 50 ma) 0.625 v < v sw3x < 0.675 v 0.7 v < v sw3x < 0.85 v 0.875 v < v sw3x < 1.975 v 2.0 v < v sw3x < 3.3 v -25 -3.0% -6.0% -65 -45 -3.0% -3.0% ? ? ? ? ? ? ? 25 3.0% 6.0% 65 45 3.0% 3.0% mv % (50) i sw3x rated output load current (51) ? 2.8 v < v in < 4.5 v, 0.625 v < v sw3x < 3.3 v pwm, aps mode single phase pwm, aps mode independent (per phase) ? ? ? ? 2500 1250 ma
nxp semiconductors 57 pf0200 functional block requirements and behaviors switch mode supply sw3a/b (continued) i sw3xlim current limiter peak current detection ? single phase (current through inductor) sw3xilim = 0 sw3xilim = 1 ? independent mode (current through inductor per phase) sw3xilim = 0 sw3xilim = 1 3.5 2.7 1.8 1.3 5.0 3.8 2.5 1.9 6.5 4.9 3.3 2.5 a v sw3xosh start-up overshoot i sw3x = 0.0 ma dvs clk = 25 mv/4 s, v in = vin sw3x = 4.5 v ??66mv ton sw3x turn-on time enable to 90% of end value i sw3x = 0 ma dvs clk = 25 mv/4 s, v in = vin sw3x = 4.5 v ? ? 500 s f sw3x switching frequency sw3xfreq[1:0] = 00 sw3xfreq[1:0] = 01 sw3xfreq[1:0] = 10 ? ? ? 1.0 2.0 4.0 ? ? ? mhz sw3ab efficiency (single phase) ?f sw3 = 2.0 mhz, l sw3x 1.0 h pfm, 1.5 v, 1.0 ma pfm, 1.5 v, 50 ma aps, pwm 1.5 v, 500 ma aps, pwm 1.5 v, 750 ma aps, pwm 1.5 v, 1250 ma aps, pwm 1.5 v, 2500 ma ? ? ? ? ? ? 84 85 85 84 80 74 ? ? ? ? ? ? % v sw3x output ripple ? 10 ? mv v sw3xlir line regulation (aps, pwm) ? ? 20 mv v sw3xlor dc load regulation (aps, pwm) ? ? 20 mv v sw3xlotr transient load regulation ? transient load = 0.0 ma to i sw3x /2, di/dt = 100 ma/ s overshoot undershoot ? ? ? ? 50 50 mv i sw3xq quiescent current pfm mode (single phase) aps mode (single phase) pfm mode (independent mode) aps mode (sw3a independent mode) aps mode (sw3b independent mode) ? ? ? ? ? 22 300 50 250 150 ? ? ? ? ? a r onsw3ap sw3a p-mosfet r dson at v in = vin sw3a = 3.3 v ? 215 245 m r onsw3an sw3a n-mosfet r dson at v in = vin sw3a = 3.3 v ? 258 326 m i sw3apq sw3a p-mosfet leakage current v in = vin sw3a = 4.5 v ??7.5a table 71. sw3a/b electrical characteristics (continued) all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], typical external component values, f sw3x = 2.0 mhz, single phase and independent mode unless, otherwise noted. ty pical values are characterized at v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. symbol p arameter min. typ. max. unit notes
58 nxp semiconductors pf0200 functional block requirements and behaviors figure 17. sw3ab single phase efficiency waveforms 6.4.5 boost regulator swbst is a boost regulator with a pr ogrammable output from 5.0 to 5.15 v. swbst can supply the vusb regulator for the usb phy in otg mode, as well as the vbus voltage. no te that the parasitic leakage path for a boost regulator will cause the swbstout and swbstfb voltage to be a schottky drop below the input voltage whenever swbst is disabl ed. the switching nmos transistor is integrated on-chip. figure 18 shows the block diagram and component connection for the boost regulator. switch mode supply sw3a/b (continued) i sw3anq sw3a n-mosfet leakage current v in = vin sw3a = 4.5 v ??2.5a r onsw3bp sw3b p-mosfet r ds(on) at v in = vin sw3b = 3.3 v ? 215 245 m r onsw3bn sw3b n-mosfet r ds(on) at v in = vin sw3b = 3.3 v ? 258 326 m i sw3bpq sw3b p-mosfet leakage current v in = vin sw3b = 4.5 v ??7.5a i sw3bpq sw3b n-mosfet leakage current v in = vin sw3b = 4.5 v ??2.5a r sw3xdis discharge resistance ? 600 ? notes 49. when output is set to > 2.6 v the output will follow the input down when v in gets near 2.8 v. 50. accuracy specification is in clusive of load and line regulation. 51. the higher output voltages available depend on the voltage dr op in the conduction path as giv en by the following equation: (vin sw3x - v sw3x ) = i sw3x * (dcr of inductor +r onsw3xp + pcb trace resistance). table 71. sw3a/b electrical characteristics (continued) all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], typical external component values, f sw3x = 2.0 mhz, single phase and independent mode unless, otherwise noted. typical values are characterized at v in = vin sw3x = 3.6 v, v sw3x = 1.5 v, i sw3x = 100 ma, sw3x_pwrstg[2:0] = [111], and 25 c, unless otherwise noted. symbol p arameter min. typ. max. unit notes 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1000 e f f i c i e n c y ( % ) load current (ma) pfm - vout = 1.5v aps - vout = 1.5v pwm - vout = 1.5v efficiency (%)
nxp semiconductors 59 pf0200 functional block requirements and behaviors figure 18. boost regulator architecture 6.4.5.1 swbst setup and control boost regulator control is done through a single register swbstctl described in table 72 . swbst is included in the power-up sequence if its otp power-up timing bits, sw bst_seq[4:0], are not all zeros. table 72. register swbstctl - addr 0x66 name bit # r/w default description swbst1volt 1:0 r/w 0x00 set the output voltage for swbst 00 = 5.000 v 01 = 5.050 v 10 = 5.100 v 11 = 5.150 v swbst1mode 3:2 r 0x02 set the switching mode on normal operation 00 = off 01 = pfm 10 = auto (default) (52) 11 = aps unused 4 ? 0x00 unused swbst1stbymode 6:5 r/w 0x02 set the switching mode on standby 00 = off 01 = pfm 10 = auto (default) (52) 11 = aps unused 7 ? 0x00 unused notes 52. in auto mode, the controller automatically swit ches between pfm and aps modes depending on the load current. the swbst regulator starts up by default in the auto mode, if swbst is part of the startup sequence. swbstlx v obst driver controller ea z1 z2 internal compensation i 2 c interface swbstmode v refuv v ref ep vin l bst c inbst d bst swbstfb r sense sc v refsc swbstfault oc uv c oswbst swbstin
60 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.5.2 swbst external components 6.4.5.3 swbst specifications table 73. swbst external component requirements components description values c inbst (53) swbst input capacitor 10 f c inbsthf (53) swbst decoupling input capacitor 0.1 f c obst (53) swbst output capacitor 2 x 22 f l sbst swbst inductor 2.2 h d bst swbst boost diode 1.0 a, 20 v schottky notes 53. use x5r or x7r capacitors. table 74. swbst elect rical specifications all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, typical external component values, f swbst = 2.0 mhz, otherwise noted. typical values are characterized at v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, and 25 c, unless otherwise noted. symbol parameters min. typ. max. units notes switch mode supply swbst vin swbst input voltage range 2.8 ? 4.5 v v swbst nominal output voltage ? table 72 ?v v swbstacc output voltage accuracy 2.8 v v in 4.5 v 0 < i swbst < iswbst max -4.0 ? 3.0 % v swbst output ripple 2.8 v v in 4.5 v 0 < i swbst < iswbst max , excluding reverse recovery of schottky diode ? ? 120 mv vp-p v swbstlor dc load regulation 0 < i swbst < iswbst max ?0.5 ?mv/ma v swbstlir dc line regulation 2.8 v v in 4.5 v, i swbst = iswbst max ? 50 ? mv i swbst continuous load current 2.8 v v in 3.0 v 3.0 v v in 4.5 v ? ? ? ? 500 600 ma i swbstq quiescent current auto ? 222 289 a r dsonbst mosfet on resistance ? 206 306 m i swbstlim peak current limit 1400 2200 3200 ma (54) v swbstosh start-up overshoot i swbst = 0.0 ma ??500mv v swbsttr transient load response i swbst from 1.0 to 100 ma in 1.0 s maximum transient amplitude ??300mv v swbsttr transient load response i swbst from 100 to 1.0 ma in 1.0 s maximum transient amplitude ??300mv
nxp semiconductors 61 pf0200 functional block requirements and behaviors 6.4.6 ldo regulators description this section describes the ldo regulators provided by the pf0200. all regulators use the main bandgap as reference. refer to bias and references block description section for further information on the internal reference voltages. a low power mode is automatically activated by reducing bias currents when the load cu rrent is less than i_lmax/5. however, th e lowest bias currents may be attained by forcing the part into its low po wer mode by setting the vgenxlpwr bit. the use of this bit is only recommended when the load is expected to be less than i_lmax/50, otherwise perf ormance may be degraded. when a regulator is disabled, the output will be discharged by an internal pull-down. the pull-down is also activated when rese tbmcu is low. figure 19. general ldo block diagram switch mode supply swbst (continued) t swbsttr transient load response i swbst from 1.0 to 100 ma in 1.0 s time to settle 80% of transient ? ? 500 s t swbsttr transient load response i swbst from 100 to 1.0 ma in 1.0 s time to settle 80% of transient ??20ms i swbsthsq nmos off leakage swbstin = 4.5 v, swbstmode [1:0] = 00 ?1.05.0a ton swbst turn-on time enable to 90% of v swbst, i swbst = 0.0 ma ??2.0ms f swbst switching frequency ? 2.0 ? mhz swbst efficiency i swbst = iswbst max ?86? % notes 54. only in auto mode. table 74. swbst electrical specifications (continued) all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, typical external component values, f swbst = 2.0 mhz, otherwise noted. typical values are characterized at v in = vin swbst = 3.6 v, v swbst = 5.0 v, i swbst = 100 ma, and 25 c, unless otherwise noted. symbol parameters min. typ. max. units notes vgenx vinx vinx vgenx c genx vgenxen vgenxlpwr v ref vgenx i 2 c interface discharge + _
62 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.6.1 transient response waveforms idealized stimulus and response waveforms for transi ent line and transient load tests are depicted in figure 20 . note that the transient line and load response refers to the overs hoot, or undershoot only, excluding the dc shift. figure 20. transient waveforms 10 us 10 us v inx transient line stimulus v inx_initial v inx_final 1.0 us 1.0 us i max /10 i max i load transient load stimulus undershoot i l = i max /10 v out v out transient load response i l = i max overshoot undershoot v out v out transient line response overshoot v inx_initial v inx_final
nxp semiconductors 63 pf0200 functional block requirements and behaviors 6.4.6.2 short-circuit protection all general purpose ldos have short-circuit protection capabilit y. the short-circuit protection (scp) system includes debounced fault condition detection, regulator shutdown, and processor interrupt gen eration, to contain failures and minimize the chance of pro duct damage. if a short-circuit condition is detec ted, the ldo will be disabled by resetti ng its vgenxen bit, while at the same time , an interrupt vgenxfaulti will be genera ted to flag the f ault to the system processor. the vgenxf aulti interrupt is maskable through the vgenxfaultm mask bit. the scp feature is enabled by setting the regs cpen bit. if this bit is not set, the regulators will not automatically be disab led upon a short-circuit detection. however, the curr ent limiter will continue to li mit the output current of th e regulator. by default, t he regscpen is not set; therefore, at start-up none of the regulators will be disabled if an overloaded condition occurs. a fault interrupt, v genxfaulti, will be generated in an overload condition regardle ss of the state of the regscpen bit. see table 75 for scp behavior configuration. 6.4.6.3 ldo regulator control each ldo is fully controlled through its respective vgenxctl regi ster. this register enables the user to set the ldo output vol tage according to table 76 for vgen1 and vgen2; and uses the voltage set point on table 77 for vgen3 th rough vgen6. table 75. short-circuit behavior regscpen[0] short-circuit behavior 0 current limit 1 shutdown table 76. vgen1, vgen2 output voltage configuration set point vgenx[3:0] vgenx output (v) 0 0000 0.800 1 0001 0.850 2 0010 0.900 3 0011 0.950 4 0100 1.000 5 0101 1.050 6 0110 1.100 7 0111 1.150 8 1000 1.200 9 1001 1.250 10 1010 1.300 11 1011 1.350 12 1100 1.400 13 1101 1.450 14 1110 1.500 15 1111 1.550
64 nxp semiconductors pf0200 functional block requirements and behaviors besides the output voltage configuration, the ldos can be enabl ed or disabled at anytime during normal mode operation, as well as programmed to stay ?on? or be disabled when the pmic enters standby mode. each regulator has associated i 2 c bits for this. table 78 presents a summary of all valid combinations of the control bits on vgenxctl register and the ex pected behavior of the ldo outp ut. for more detail information, table 79 through table 84 provide a description of all registers ne cessary to operate all six general purpose ldo regulators. table 77. vgen3/ 4/ 5/ 6 output voltage configuration set point vgenx[3:0] vgenx output (v) 00000 1.80 10001 1.90 20010 2.00 30011 2.10 40100 2.20 50101 2.30 60110 2.40 70111 2.50 81000 2.60 91001 2.70 10 1010 2.80 11 1011 2.90 12 1100 3.00 13 1101 3.10 14 1110 3.20 15 1111 3.30 table 78. ldo control vgenxen vgenxlpwr vgenxstby standby (55) vgenxout 0x xxoff 10 0xon 1 1 0 x low power 1x 10on 10 11off 1 1 1 1 low power notes 55. standby refers to a standby event as described earlier.
nxp semiconductors 65 pf0200 functional block requirements and behaviors table 79. register vgen1ctl - addr 0x6c name bit # r/w default description vgen1 3:0 r/w 0x80 sets vgen1 output voltage. see table 76 for all possible configurations. vgen1en 4 ? 0x00 enables or disables vgen1 output 0 = off 1 = on vgen1stby 5 r/w 0x00 set vgen1 output state when in standby. refer to table 78 . vgen1lpwr 6 r/w 0x00 enable low power mode for vgen1. refer to table 78 . unused 7 ? 0x00 unused table 80. register vgen2ctl - addr 0x6d name bit # r/w default description vgen2 3:0 r/w 0x80 sets vgen2 output voltage. see table 76 for all possible configurations. vgen2en 4 ? 0x00 enables or disables vgen2 output 0 = off 1 = on vgen2stby 5 r/w 0x00 set vgen2 output state when in standby. refer to table 78 . vgen2lpwr 6 r/w 0x00 enable low power mode for vgen2. refer to table 78 . unused 7 ? 0x00 unused table 81. register vgen3ctl - addr 0x6e name bit # r/w default description vgen3 3:0 r/w 0x80 sets vgen3 output voltage. see table 77 for all possible configurations. vgen3en 4 ? 0x00 enables or disables vgen3 output 0 = off 1 = on vgen3stby 5 r/w 0x00 set vgen3 output state when in standby. refer to table 78 . vgen3lpwr 6 r/w 0x00 enable low power mode for vgen3. refer to table 78 . unused 7 ? 0x00 unused
66 nxp semiconductors pf0200 functional block requirements and behaviors table 82. register vgen4ctl - addr 0x6f name bit # r/w default description vgen4 3:0 r/w 0x80 sets vgen4 output voltage. see table 77 for all possible configurations. vgen4en 4 ? 0x00 enables or disables vgen4 output 0 = off 1 = on vgen4stby 5 r/w 0x00 set vgen4 output state when in standby. refer to table 78 . vgen4lpwr 6 r/w 0x00 enable low power mode for vgen4. refer to table 78 . unused 7 ? 0x00 unused table 83. register vgen5ctl - addr 0x70 name bit # r/w default description vgen5 3:0 r/w 0x80 sets vgen5 output voltage. see table 77 for all possible configurations. vgen5en 4 ? 0x00 enables or disables vgen5 output 0 = off 1 = on vgen5stby 5 r/w 0x00 set vgen5 output state when in standby. refer to table 78 . vgen5lpwr 6 r/w 0x00 enable low power mode for vgen5. refer to table 78 . unused 7 ? 0x00 unused table 84. register vgen6ctl - addr 0x71 name bit # r/w default description vgen6 3:0 r/w 0x80 sets vgen6 output voltage. see table 77 for all possible configurations. vgen6en 4 ? 0x00 enables or disables vgen6 output 0 = off 1 = on vgen6stby 5 r/w 0x00 set vgen6 output state when in standby. refer to table 78 . vgen6lpwr 6 r/w 0x00 enable low power mode for vgen6. refer to table 78 . unused 7 ? 0x00 unused
nxp semiconductors 67 pf0200 functional block requirements and behaviors 6.4.6.4 external components table 85 lists the typical component values fo r the general purpose ldo regulators. 6.4.6.5 ldo specifications vgen1 table 85. ldo external components regulator output capacitor ( f) (56) vgen1 2.2 vgen2 4.7 vgen3 2.2 vgen4 4.7 vgen5 2.2 vgen6 2.2 notes 56. use x5r/x7r ce ramic capacitors. table 86. vgen1 electrical characteristics all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6 v, in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes vgen1 v in1 operating input voltage 1.75 ? 3.40 v vgen1 nom nominal output voltage ? table 76 ?v i gen1 operating load current 0.0 ? 100 ma vgen1 dc v gen1tol output voltage tolerance 1.75 v < v in1 < 3.4 v 0.0 ma < i gen1 < 100 ma vgen1[3:0] = 0000 to 1111 -3.0 ? 3.0 % v gen1lor load regulation (v gen1 at i gen1 = 100 ma) - (v gen1 at i gen1 = 0.0 ma) for any 1.75 v < v in1 < 3.4 v ? 0.15 ? mv/ma v gen1lir line regulation (v gen1 at v in1 = 3.4 v) - (v gen1 at v in1 = 1.75 v) for any 0.0 ma < i gen1 < 100 ma ? 0.30 ? mv/ma i gen1lim current limit i gen1 when vgen1 is forced to vgen1 nom /2 122 167 200 ma i gen1ocp overcurrent protection threshold i gen1 required to cause the scp function to disable ldo when regscpen = 1 115 ? 200 ma i gen1q quiescent current no load, change in i vin and i vin1 when vgen1 enabled ?14? a
68 nxp semiconductors pf0200 functional block requirements and behaviors vgen1 ac and transient psrr vgen1 psrr ?i gen1 = 75 ma, 20 hz to 20 khz vgen1[3:0] = 0000 - 1101 vgen1[3:0] = 1110, 1111 50 37 60 45 ? ? db (57) noise vgen1 output noise density v in1 = 1.75 v, i gen1 = 75 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz ? ? ? -108 -118 -124 -100 -108 -112 dbv/ hz slwr vgen1 turn-on slew rate ? 10% to 90% of end value ? 1.75 v v in1 3.4 v, i gen1 = 0.0 ma vgen1[3:0] = 0000 to 0111 vgen1[3:0] = 1000 to 1111 ? ? ? ? 12.5 16.5 mv / s gen1 ton turn-on time enable to 90% of end value, v in1 = 1.75 v, 3.4 v i gen1 = 0.0 ma 60 ? 500 s gen1 toff turn-off time disable to 10% of initial value, v in1 = 1.75 v i gen1 = 0.0 ma ??10ms gen1 osht start-up overshoot v in1 = 1.75 v, 3.4 v, i gen1 = 0.0 ma ?1.02.0% v gen1lotr transient load response ?v in1 = 1.75 v, 3.4 v i gen1 = 10 to 100 ma in 1.0 s. peak of overshoot or undershoot of vgen1 with respect to final value ? refer to figure 20 ??3.0% v gen1litr transient line response ?i gen1 = 75 ma vin1 initial = 1.75 v to vin1 final = 2.25 v for vgen1[3:0] = 0000 to 1101 vin1 initial = v gen1 +0.3 v to vin1 final = v gen1 +0.8 v for vgen1[3:0] = 1110, 1111 ? refer to figure 20 ?5.08.0mv notes 57. the psrr of the regulators is measured with the perturbing si gnal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the pertur bed signal. during measurements, care must be taken not to opera te in the dropout region of the regulator under test. table 86. vgen1 electrical characteristics (continued) all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6 v, in1 = 3.0 v, v gen1 [3:0] = 1111, i gen1 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
nxp semiconductors 69 pf0200 functional block requirements and behaviors vgen2 table 87. vgen2 electrical characteristics all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in1 = 3.0 v, v gen2 [3:0] = 1111, i gen2 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6v, v in1 = 3.0 v, vgen2[3:0] = 1111, i gen2 = 10ma and 25c, unless otherwise noted. symbol parameter min. typ. max. unit notes vgen2 v in1 operating input voltage 1.75 ? 3.40 v vgen2 nom nominal output voltage ? table 76 ?v i gen2 operating load current 0.0 ? 250 ma vgen2 active mode - dc v gen2tol output voltagetolerance 1.75 v < v in1 < 3.4 v 0.0 ma < i gen2 < 250 ma vgen2[3:0] = 0000 to 1111 -3.0 ? 3.0 % v gen2lor load regulation (v gen2 at i gen2 = 250 ma) - (v gen2 at i gen2 = 0.0 ma) for any 1.75 v < v in1 < 3.4 v ? 0.05 ? mv/ma v gen2lir line regulation (v gen2 at v in1 = 3.4 v) - (v gen2 at v in1 = 1.75 v) for any 0.0 ma < i gen2 < 250 ma ?0.50?mv/ma i gen2lim current limit i gen2 when vgen2 is forced to vgen2 nom /2 305 417 510 ma i gen2ocp over-current protection threshold i gen2 required to cause the scp function to disable ldo when regscpen = 1 290 ? 500 ma i gen2q quiescent current no load, change in i vin and i vin1 when vgen2 enabled ?16? a vgen2 ac and transient psrr vgen2 psrr ?i gen2 = 187.5 ma, 20 hz to 20 khz vgen2[3:0] = 0000 - 1101 vgen2[3:0] = 1110, 1111 50 37 60 45 ? ? db (58) noise vgen2 output noise density ?v in1 = 1.75 v, i gen2 = 187.5 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz ? ? ? -108 -118 -124 -100 -108 -112 dbv/ hz slwr vgen2 turn-on slew rate ? 10% to 90% of end value ?1.75 v v in1 3.4 v , i gen2 = 0.0 ma vgen2[3:0] = 0000 to 0111 vgen2[3:0] = 1000 to 1111 ? ? ? ? 12.5 16.5 mv / s gen2 ton turn-on time enable to 90% of end value, v in1 = 1.75 v, 3.4 v i gen2 = 0.0 ma 60 ? 500 s gen2 toff turn-off time disable to 10% of initial value, v in1 = 1.75 v i gen2 = 0.0 ma ??10ms
70 nxp semiconductors pf0200 functional block requirements and behaviors vgen2 ac and transient (continued) gen2 osht start-up overshoot v in1 = 1.75 v, 3.4 v, i gen2 = 0.0 ma ?1.02.0% v gen2lotr transient load response v in1 = 1.75 v, 3.4 v i gen2 = 25 to 250 ma in 1.0 s peak of overshoot or undershoot of vgen2 with respect to final value refer to figure 20 ??3.0% v gen2litr transient line response i gen2 = 187.5 ma vin1 initial = 1.75 v to vin1 final = 2.25 v for vgen2[3:0] = 0000 to 1101 vin1 initial = v gen2 +0.3 v to vin1 final = v gen2 +0.8 v for vgen2[3:0] = 1110, 1111 refer to figure 20 ?5.08.0mv notes 58. the psrr of the regulators is measured with the perturbing sig nal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the perturbed signal. during measurements, care must be taken not to opera te in the dropout region of the regulator under test. table 87. vgen2 electrical characteristics (continued) all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in1 = 3.0 v, v gen2 [3:0] = 1111, i gen2 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6v, v in1 = 3.0 v, vgen2[ 3:0] = 1111, i gen2 = 10ma and 25c, unless otherwise noted. symbol parameter min. typ. max. unit notes
nxp semiconductors 71 pf0200 functional block requirements and behaviors vgen3 table 88. vgen3 electrical characteristics all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, typical external component values, unless other wise noted. typical valu es are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit vgen3 v in2 operating input voltage 1.8 v vgen3 nom 2.5 v 2.6 v vgen3 nom 3.3 v 2.8 vgen3 no m + 0.250 ? ? 3.6 3.6 v (59) vgen3 nom nominal output voltage ? table 77 ?v i gen3 operating load current 0.0 ? 100 ma vgen3 dc v gen3tol output voltage tolerance vin2 min < v in2 < 3.6 v 0.0 ma < i gen3 < 100 ma vgen3[3:0] = 0000 to 1111 -3.0 ? 3.0 % v gen3lor load regulation (v gen3 at i gen3 = 100 ma) - (v gen3 at i gen3 = 0.0 ma) for any vin2 min < v in2 < 3.6 v ?0.07?mv/ma v gen3lir line regulation (v gen3 at v in2 = 3.6 v) - (v gen3 at vin2 min ) for any 0.0 ma < i gen3 < 100 ma ?0.8?mv/ma i gen3lim current limit i gen3 when vgen3 is forced to vgen3 nom /2 127 167 200 ma i gen3ocp overcurrent protection threshold i gen3 required to cause the scp function to disable ldo when regscpen = 1 120 ? 200 ma i gen3q quiescent current no load, change in i vin and i vin2 when vgen3 enabled ?13? a vgen3 ac and transient psrr vgen3 psrr ?i gen3 = 75 ma, 20 hz to 20 khz vgen3[3:0] = 0000 - 1110, v in2 = vin2 min + 100 mv vgen3[3:0] = 0000 - 1000, v in2 = vgen3 nom + 1.0 v 35 55 40 60 ? ? db (60) noise vgen3 output noise density ?v in2 = vin2 min , i gen3 = 75 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz ? ? ? -114 -129 -135 -102 -123 -130 dbv/ hz slwr vgen3 turn-on slew rate ? 10% to 90% of end value ?vin2 min v in2 3.6 v , i gen3 = 0.0 ma vgen3[3:0] = 0000 to 0011 vgen3[3:0] = 0100 to 0111 vgen3[3:0] = 1000 to 1011 vgen3[3:0] = 1100 to 1111 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv / s gen3 ton turn-on time enable to 90% of end value, v in2 = vin2 min , 3.6 v i gen3 = 0.0 ma 60 ? 500 s
72 nxp semiconductors pf0200 functional block requirements and behaviors vgen4 vgen3 ac and transient (continued) gen3 toff turn-off time disable to 10% of initial value, v in2 = vin2 min i gen3 = 0.0 ma ??10ms gen3 osht start-up overshoot v in2 = vin2 min , 3.6 v, i gen3 = 0.0 ma ?1.02.0% v gen3lotr transient load response v in2 = vin2 min , 3.6 v i gen3 = 10 to 100 ma in 1.0 s peak of overshoot or undershoot of vgen3 with respect to final value. refer to figure 20 ??3.0% v gen3litr transient line response i gen3 = 75 ma vin2 initial = 2.8 v to vin2 final = 3.3 v for gen3[3:0] = 0000 to 0111 vin2 initial = v gen3 +0.3 v to vin2 final = v gen3 +0.8 v for vgen3[3:0] = 1000 to 1010 vin2 initial = v gen3 +0.25 v to vin2 final = 3.6 v for vgen3[3:0] = 1011 to 1111 refer to figure 20 ?5.08.0mv notes 59. when the ldo output voltage is set above 2.6 v, the minimum allowed input voltage needs to be at least the output voltage pl us 0.25 v, for proper regulation due to the dropout voltage generated through the internal ldo transistor. 60. the psrr of the regulators is measured with the perturbing si gnal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the pertur bed signal. during measurements, care must be taken not to opera te in the dropout region of the regulator under test. vin2 min refers to the minimum allowed input voltage for a particular output voltage. table 89. vgen4 electr ical characteristics all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes vgen4 v in2 operating input voltage 1.8 v vgen4 nom 2.5 v 2.6 v vgen4 nom 3.3 v 2.8 vgen4 no m + 0.250 ? ? 3.6 3.6 v (61) vgen4 nom nominal output voltage ? table 77 ?v i gen4 operating load current 0.0 ? 350 ma vgen4 dc v gen4tol output voltage tolerance vin2 min < v in2 < 3.6 v 0.0 ma < i gen4 < 350 ma vgen4[3:0] = 0000 to 1111 -3.0 ? 3.0 % v gen4lor load regulation (v gen4 at i gen4 = 350 ma) - (v gen4 at i gen4 = 0.0 ma ) for any vin2 min < v in2 < 3.6 v ?0.07?mv/ma table 88. vgen3 electrical characteristics (continued) all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen3 [3:0] = 1111, i gen3 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit
nxp semiconductors 73 pf0200 functional block requirements and behaviors vgen4 dc (continued) v gen4lir line regulation (v gen4 at 3.6 v) - (v gen4 at vin2 min ) for any 0.0 ma < i gen4 < 350 ma ? 0.80 ? mv/ma i gen4lim current limit i gen4 when vgen4 is forced to vgen4 nom /2 435 584.5 700 ma i gen4ocp overcurrent protection threshold i gen4 required to cause the scp function to disable ldo when regscpen = 1 420 ? 700 ma i gen4q quiescent current no load, change in i vin and i vin2 when vgen4 enabled ?13? a vgen4 ac and transient psrr vgen4 psrr ?i gen4 = 262.5 ma, 20 hz to 20 khz vgen4[3:0] = 0000 - 1110, v in2 = vin2 min + 100 mv vgen4[3:0] = 0000 - 1000, v in2 = vgen4 nom + 1.0 v 35 55 40 60 ? ? db (62) noise vgen4 output noise density ?v in2 = vin2 min , i gen4 = 262.5 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz ? ? ? -114 -129 -135 -102 -123 -130 dbv/ hz slwr vgen4 turn-on slew rate ? 10% to 90% of end value ?vin2 min v in2 3.6 v , i gen4 = 0.0 ma vgen4[3:0] = 0000 to 0011 vgen4[3:0] = 0100 to 0111 vgen4[3:0] = 1000 to 1011 vgen4[3:0] = 1100 to 1111 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv / s gen4 ton turn-on time enable to 90% of end value, v in2 = vin2 min , 3.6 v i gen4 = 0.0 ma 60 ? 500 s gen4 toff turn-off time disable to 10% of initial value, v in2 = vin2 min i gen4 = 0.0 ma ??10ms gen4 osht start-up overshoot v in2 = vin2 min , 3.6 v, i gen4 = 0.0 ma ?1.02.0% v gen4lotr transient load response v in2 = vin2 min , 3.6 v i gen4 = 35 to 350 ma in 1.0 s peak of overshoot or undershoot of vgen4 with respect to final value. refer to figure 20 ??3.0% table 89. vgen4 electrical characteristics (continued) all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, typical external component values, unless other wise noted. typical valu es are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
74 nxp semiconductors pf0200 functional block requirements and behaviors vgen5 vgen4 ac and transient (continued) v gen4litr transient line response i gen4 = 262.5 ma vin2 initial = 2.8 v to vin2 final = 3.3 v for vgen4[3:0] = 0000 to 0111 vin2 initial = v gen4 +0.3 v to vin2 final = v gen4 +0.8 v for vgen4[3:0] = 1000 to 1010 vin2 initial = v gen4 +0.25 v to vin2 final = 3.6 v for vgen4[3:0] = 1011 to 1111 refer to figure 20 ?5.08.0mv notes 61. when the ldo output voltage is set above 2.6 v the minimum al lowed input voltage need to be at least the output voltage plus 0.25 v for proper regulation due to the dropout voltage generated through the internal ldo transistor. 62. the psrr of the regulators is measured with the perturbing si gnal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the pertur bed signal. during measurements, care must be taken not to opera te in the dropout region of the regulator under test. vin2 min refers to the minimum allowed input voltage for a particular output voltage. table 90. vgen5 electr ical characteristics all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6 v, vin3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes vgen5 v in3 operating input voltage 1.8 v vgen5 nom 2.5 v 2.6 v vgen5 nom 3.3 v 2.8 vgen5 no m + 0.250 ? ? 4.5 4.5 v (63) vgen5 nom nominal output voltage ? table 77 ?v i gen5 operating load current 0.0 ? 100 ma vgen5 active mode ? dc v gen5tol output voltage tolerance vin3 min < v in3 < 4.5 v 0.0 ma < i gen5 < 100 ma vgen5[3:0] = 0000 to 1111 -3.0 ? 3.0 % v gen5lor load regulation (v gen5 at i gen5 = 100 ma) - (v gen5 at i gen5 = 0.0 ma) for any vin3 min < v in3 < 4.5 mv ?0.10?mv/ma v gen5lir line regulation (v gen5 at v in3 = 4.5 v) - (v gen5 at vin3 min ) for any 0.0 ma < i gen5 < 100 ma ?0.50?mv/ma i gen5lim current limit i gen5 when vgen5 is forced to vgen5 nom /2 122 167 200 ma i gen5ocp overcurrent protection threshold i gen5 required to cause the scp function to disable ldo when regscpen = 1 120 ? 200 ma table 89. vgen4 el ectrical characteri stics (continued) all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6 v, v in2 = 3.6 v, v gen4 [3:0] = 1111, i gen4 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
nxp semiconductors 75 pf0200 functional block requirements and behaviors vgen5 active mode ? dc (continued) i gen5q quiescent current no load, change in i vin and i vin3 when vgen5 enabled ?13? a vgen5 ac and transient psrr vgen5 psrr ?i gen5 = 75 ma, 20 hz to 20 khz vgen5[3:0] = 0000 - 1111, v in3 = vin3 min + 100 mv vgen5[3:0] = 0000 - 1111, v in3 = vgen5 nom + 1.0 v 35 52 40 60 ? ? db (64) noise vgen5 output noise density ?v in3 = vin3 min , i gen5 = 75 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz ? ? ? -114 -129 -135 -102 -123 -130 dbv/ hz slwr vgen5 turn-on slew rate ? 10% to 90% of end value ?vin3 min v in3 4.5 mv , i gen5 = 0.0 ma vgen5[3:0] = 0000 to 0011 vgen5[3:0] = 0100 to 0111 vgen5[3:0] = 1000 to 1011 vgen5[3:0] = 1100 to 1111 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv / s gen5 ton turn-on time enable to 90% of end value, v in3 = vin3 min , 4.5 v i gen5 = 0.0 ma 60 ? 500 s gen5 toff turn-off time disable to 10% of initial value, v in3 = vin3 min i gen5 = 0.0 ma ??10ms gen5 osht start-up overshoot v in3 = vin3 min , 4.5 v, i gen5 = 0.0 ma ?1.02.0% v gen5lotr transient load response v in3 = vin3 min , 4.5 v i gen5 = 10 to 100 ma in 1.0 s peak of overshoot or undershoot of vgen5 with respect to final value. refer to figure 20 ??3.0% v gen5litr transient line response i gen5 = 75 ma vin3 initial = 2.8 v to vin3 final = 3.3 v for vgen5[3:0] = 0000 to 0111 vin3 initial = v gen5 +0.3 v to vin3 final = v gen5 +0.8 v for vgen5[3:0] = 1000 to 1111 refer to figure 20 -5.08.0mv notes 63. when the ldo output voltage is set above 2.6 v the minimum allowed input voltage need to be at least the output voltage plus 0.25 v for proper regulation due to the dropout voltage generated through the internal ldo transistor. 64. the psrr of the regulators is measured with the perturbing si gnal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the pertur bed signal. during measurements, care must be taken not to opera te in the dropout region of the regulator under test. vin3 min refers to the minimum allowed input voltage for a particular output voltage. table 90. vgen5 electrical characteristics (continued) all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, typical external component values, unless other wise noted. typical valu es are characterized at v in = 3.6 v, vin3 = 3.6 v, v gen5 [3:0] = 1111, i gen5 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
76 nxp semiconductors pf0200 functional block requirements and behaviors vgen6 table 91. vgen6 electr ical characteristics all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, typical external component values, unless ot herwise noted. typical values are characterized at v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes vgen6 v in3 operating input voltage 1.8 v vgen6 nom 2.5 v 2.6 v vgen6 nom 3.3 v 2.8 vgen6 no m + 0.250 ? ? 4.5 4.5 v (65) vgen6 nom nominal output voltage ? table 77 ?v i gen6 operating load current 0.0 ? 200 ma vgen6 dc v gen6tol output voltage tolerance vin3 min < v in3 < 4.5 v 0.0 ma < i gen6 < 200 ma vgen6[3:0] = 0000 to 1111 -3.0 ? 3.0 % v gen6lor load regulation (v gen6 at i gen6 = 200 ma) - (v gen6 at i gen6 = 0.0 ma) for any vin3 min < v in3 < 4.5 v ?0.10?mv/ma v gen6lir line regulation (v gen6 at v in3 = 4.5 v) - (v gen6 at vin3 min ) for any 0.0 ma < i gen6 < 200 ma ?0.50?mv/ma i gen6lim current limit i gen6 when vgen6 is forced to vgen6 nom /2 232 333 475 ma i gen6ocp overcurrent protection threshold i gen6 required to cause the scp function to disable ldo when regscpen = 1 220 ? 475 ma i gen6q quiescent current no load, change in i vin and i vin3 when vgen6 enabled ?13? a vgen6 ac and transient psrr vgen6 psrr ?i gen6 = 150 ma, 20 hz to 20 khz vgen6[3:0] = 0000 - 1111, v in3 = vin3 min + 100 mv vgen6[3:0] = 0000 - 1111, v in3 = vgen6 nom + 1.0 v 35 52 40 60 ? ? db (66) noise vgen6 output noise density ?v in3 = vin3 min , i gen6 = 150 ma 100 hz ? <1.0 khz 1.0 khz ? <10 khz 10 khz ? 1.0 mhz ? ? ? -114 -129 -135 -102 -123 -130 dbv/ hz slwr vgen6 turn-on slew rate ? 10% to 90% of end value ?vin3 min v in3 4.5 v . i gen6 = 0.0 ma vgen6[3:0] = 0000 to 0011 vgen6[3:0] = 0100 to 0111 vgen6[3:0] = 1000 to 1011 vgen6[3:0] = 1100 to 1111 ? ? ? ? ? ? ? ? 22.0 26.5 30.5 34.5 mv / s gen6 ton turn-on time enable to 90% of end value, v in3 = vin3 min , 4.5 v i gen6 = 0.0 ma 60 ? 500 s
nxp semiconductors 77 pf0200 functional block requirements and behaviors 6.4.7 vsnvs ldo/switch vsnvs powers the low power, snvs/rtc domain on the processor. it de rives its power from either vin, or coin cell, and cannot b e disabled. when powered by both, vin takes precedence when above the appropriate comp arator threshold. when powered by vin, vsnvs is an ldo capable of supplying seven voltages : 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 v. the bits vsnvsvolt[2:0] in register vsnvs_control determine the output voltage. when powered by coin cell, vsnvs is an ldo capable of supplying 1.8, 1.5, 1.3, 1.2, 1.1, or 1.0 v as shown in table 92 . if the 3.0 v option is chosen with the coin cell, vsnvs tracks the coin cell voltage by means of a switch, whose maximum resistance is 100 . in this case, the vsnvs voltage is simply the coin cell voltage minus the voltage drop across the switch, which is 40 mv at a rated maximum load current of 400 a. the default setting of the vsnvsvolt[2:0] is 110, or 3.0 v, unless programmed otherwise in otp. however, when the coin cell is applied for the very first time, vsnvs will output 1.0 v. only when vin is applied thereafter will vsn vs transition to its default, or programmed value if different. upon subsequent removal of vin, with the coin cell attached, vsnvs will change configuration from an ldo to a switch for the ?110? setting, and will remain as an ldo for the other settings, continuing to output the same voltages as when vin is applied, providing certain conditions are met as described in table 92 . vgen6 ac and transient (continued) gen6 toff turn-off time disable to 10% of initial value, v in3 = vin3 min i gen6 = 0.0 ma ??10ms gen6 osht start-up overshoot v in3 = vin3 min , 4.5 v, i gen6 = 0 ma ?1.02.0% v gen6lotr transient load response v in3 = vin3 min , 4.5 v i gen6 = 20 to 200 ma in 1.0 s peak of overshoot or undershoot of vgen6 with respect to final value. refer to figure 20 ??3.0% v gen6litr transient line response i gen6 = 150 ma vin3 initial = 2.8 v to vin3 final = 3.3 v for vgen6[3:0] = 0000 to 0111 vin3 initial = v gen6 +0.3 v to vin3 final = v gen6 +0.8 v for vgen6[3:0] = 1000 to 1111 refer to figure 20 ?5.08.0mv notes 65. when the ldo output voltage is set above 2.6 v the minimum allowed input voltage need to be at least the output voltage plus 0.25 v for proper regulation due to the dropout voltage generated through the internal ldo transistor. 66. the psrr of the regulators is measured with the perturbing si gnal at the input of the regulator. the power management ic is supplied separately from the input of the regulator and does not contain the pertur bed signal. during measurements, care must be taken not to opera te in the dropout region of the regulator under test. vin3 min refers to the minimum allowed input voltage for a particular output voltage. table 91. vgen6 electrical characteristics (continued) all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, typical external component values, unless other wise noted. typical valu es are characterized at v in = 3.6 v, v in3 = 3.6 v, v gen6 [3:0] = 1111, i gen6 = 10 ma, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
78 nxp semiconductors pf0200 functional block requirements and behaviors figure 21. vsnvs supply switch architecture table 92 provides a summary of the vsnvs operation at different input volt age vin and with or without coin cell connected to the system. vsnvs control the vsnvs output level is configured through the vsnvsvolt [2:0]bits on vsnvsctl register as shown in table table 93 . vsnvs external components table 92. vsnvs modes of operation vsnvsvolt[2:0] vin mode 110 > vth1 vin ldo 3.0 v 110 < vtl1 coin cell switch 000 ? 101 > vth0 vin ldo 000 ? 101 < vtl0 coin cell ldo table 93. register vsnvsctl - addr 0x6b name bit # r/w default description vsnvsvolt 2:0 r/w 0x80 configures vsnvs output voltage. (67) 000 = 1.0 v 001 = 1.1 v 010 = 1.2 v 011 = 1.3 v 100 = 1.5 v 101 = 1.8 v 110 = 3.0 v 111 = rsvd unused 7:3 ? 0x00 unused notes 67. only valid when a valid input voltage is present. table 94. vsnvs ex ternal components capacitor value ( f) vsnvs 0.47 ldo\ pf0200 vsnvs coin cell 1.8 - 3.3 v v in 2.25 v (vtl0) - 4.5 v licell charger ldo/switch v ref + _ z input sense/ selector i 2 c interface
nxp semiconductors 79 pf0200 functional block requirements and behaviors vsnvs specifications table 95. vsnvs electrical characteristics all parameters are spec ified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 a, typical external component values, unless other wise noted. typical values are characterized at v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 a, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes vsnvs vin snvs operating input voltage valid coin cell range valid v in 1.8 2.25 ? ? 3.3 4.5 v i snvs operating load current v inmin < v in < v inmax 5.0 ? 400 a vsnvs dc, ldo v snvs output voltage ?5.0 a < i snvs < 400 a (off) 3.20 v < v in < 4.5 v, vsnvsvolt[2:0] = 110 vtl0/vth < v in < 4.5 v, vsnvsvolt[2:0] = [000] - [101] ?5.0 a < i snvs < 400 a (on) 3.20 v < v in < 4.5 v, vsnvsvolt[2:0] = 110 uvdet < v in < 4.5 v, vsnvsvolt[2:0] = [000] - [101] ?5 . 0 a < i snvs < 400 a (coin cell mode) 2.84 v < v coin < 3.3 v, vsnvsvolt[2:0] = 110 1.8 v < v coin < 3.3 v, vsnvsvolt[2:0] = [000] - [101] -5.0% -8.0% -5.0% -4.0% v coin -0.04 -8.0% 3.0 1.0 - 1.8 3.0 1.0 - 1.8 ? 1.0 - 1.8 7.0% 7.0% 5.0% 4.0% v coin 7.0% v vsnvs drop dropout voltage v in = v coin = 2.85 v, vsnvsvolt[2:0] = 110, i snvs = 400 a ??50mv isnvs lim current limit v in > v th1 , vsnvsvolt[2:0] = 110 v in > v th0 , vsnvsvolt[2:0] = 000 to 101 v in < v tl0 , vsnvsvolt[2:0] = 000 to 101 1100 500 480 ? ? ? 6750 6750 4500 a v th0 v in threshold (coin cell powered to v in powered) v in going high with valid coin cell vsnvsvolt[2:0] = 000, 001, 010, 011, 100, 101 2.25 2.40 2.55 v v tl0 v in threshold (v in powered to coin cell powered) v in going low with valid coin cell vsnvsvolt[2:0] = 000, 001, 010, 011, 100, 101 2.20 2.35 2.50 v v hyst1 v in threshold hysteresis for v th1 -v tl1 5.0 ? ? mv v hyst0 v in threshold hysteresis for v th0 -v tl0 5.0 ? ? mv vsnvs cross output voltage during crossover vsnvsvolt[2:0] = 110 v coin > 2.9 v switch to ldo: v in > 2.825 v, i snvs = 100 a ldo to switch: v in < 3.05 v, i snvs = 100 a 2.70 ? ? v (68) notes 68. during crossover from vin to licell, the vsnvs output voltage may drop to 2.7 v before going to the licell voltage. though t his is outside the specified dc voltage level for the vdd_snvs_in pin of the i.mx 6, this momentary drop does not cause any malfunction. the i.mx 6?s rtc continues to operate through the transition, and as a worst case it may switch to the internal rc oscillator for a few clock cy cles before switching back to the external crystal oscillator.
80 nxp semiconductors pf0200 functional block requirements and behaviors 6.4.7.1 coin cell battery backup the licell pin provides for a connection of a coin cell back up battery or a ?super? capacitor. if the voltage at vin goes below the v in threshold (v tl1 and v tl0 ), contact-bounced, or remo ved, the coin cell maintained logic will be powered by the voltage applied to licell. the supply for internal logic and the vsnvs rail will switch over to the licell pin when vin goes below vtl1 or vtl0, even in t he absence of a voltage at the lice ll pin, resulting in clearing of memory and tu rning off of vsnvs. when system operation below v tl1 is required, for systems not utilizing a coin cell, connect the licell pin to any system voltage between 1. 8 and 3.0 v. a small capacitor should be placed from licell to ground under all circumstances. vsnvs ac and transient ton snvs turn-on time (load capacitor, 0.47 f) v in > uvdet to 90% of v snvs v coin = 0.0 v, i snvs = 5.0 a vsnvsvolt[2:0] = 000 to 110 ??24 ms (70) , (71) v snvsosh start-up overshoot vsnvsvolt[2:0] = 000 to 110 i snvs = 5.0 a dv in /dt = 50 mv/ s ?4070mv v snvslitr transient line response i snvs = 75% of isnvs max 3.2 v < v in < 4.5 v, vsnvsvolt[2:0] = 110 2.45 v < v in < 4.5 v, vsnvsvolt[2:0] = [000] - [101] ? ? 32 22 ? ? mv v snvslotr transient load response vsnvsvolt[2:0] = 110 3.1 v (uvdetl)< v in 4.5 v i snvs = 75 to 750 a vsnvsvolt[2:0] = 000 to 101 2.45 v < v in 4.5 v vtl0 > v in , 1.8 v v coin 3.3 v i snvs = 40 to 400 a refer to figure 20 2.8 ? ? 1.0 ? 2.0 v % vsnvs dc, switch v insnvs operating input voltage valid coin cell range 1.8?3.3v i snvs operating load current 5.0 ? 400 a r dsonsnvs internal switch r ds(on) v coin = 2.6 v ? ? 100 vtl1 v in threshold (v in powered to coin cell powered) vsnvsvolt[2:0] = 110 2.725 2.90 3.00 v (72) vth1 v in threshold (coin cell powered to v in powered) vsnvsvolt[2:0] = 110 2.775 2.95 3.1 v notes 69. for 1.8 v i snvs limited to 100 a for v coin < 2.1 v 70. the start-up of vsnvs is not monotonic. it first rises to 1.0 v and then settles to its programmed value within the specifie d t r1 time. 71. from coin cell insertion to vsnvs =1.0 v, the delay time is typically 400 ms. 72. during crossover from vin to licell, the vsnvs output voltage may drop to 2.7 v before going to the licell voltage. though t his is outside the specified dc voltage level for the vdd_snvs_in pin of the i.mx 6, this momentary drop does not cause any malfunction. the i.mx 6?s rtc continues to operate through the transition, and as a worst case it may switch to the internal rc oscillator for a few clock cy cles before switching back to the external crystal oscillator. table 95. vsnvs electrical characteristics (continued) all parameters are specified at consumer t a = -40 to 85 c and extended industrial t a = -40 to 105 c, v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 a, typical external component values, unless other wise noted. typical values are characterized at v in = 3.6 v, v snvs = 3.0 v, i snvs = 5.0 a, and 25 c, unless otherwise noted. symbol parameter min. typ. max. unit notes
nxp semiconductors 81 pf0200 functional block requirements and behaviors coin cell charger control the coin cell charger circuit will function as a current-limit ed voltage source, resulting in th e cc/cv taper characteristic ty pically used for rechargeable lithium-ion batteries. the coin cell charger is enabl ed via the coinchen bit while the coin cell voltage is progra mmable through the vcoin[2:0] bits on register coinctl on table 97 . the coin cell charger voltage is programmable. in the on state, the charger current is fixed at icoinhi. in sleep and standby modes, the charger current is reduced to a typical 10 a. in the off state, coin cell charging is not available as the main battery could be depleted unnecessarily. the coin cell charging will be stopped when v in is below uvdet. external components coin cell specifications table 96. coin cell charger voltage vcoin[2:0] v coin (v) (73) 000 2.50 001 2.70 010 2.80 011 2.90 100 3.00 101 3.10 110 3.20 111 3.30 notes 73. coin cell voltages selected based on the type of licell used on the system. table 97. register coinctl - addr 0x1a name bit # r/w default description vcoin 2:0 r/w 0x00 coin cell charger output voltage selection. see table 96 for all options selectable through these bits. coinchen 3 r/w 0x00 enable or disable the coin cell charger unused 7:4 ? 0x00 unused table 98. coin cell charger external components component value units licell bypass capacitor 100 nf table 99. coin cell charger specifications parameter typ unit voltage accuracy 100 mv coin cell charge current in on mode icoinhi 60 a current accuracy 30 %
82 nxp semiconductors pf0200 functional block requirements and behaviors 6.5 control interface i 2 c block description the pf0200 contains an i 2 c interface port which allows access by a processor, or any i 2 c master, to the register set. via these registers the resources of the ic can be controlled. the registers also provide status info rmation about how the ic is operating. the scl and sda lines should be routed away from noisy signals and planes to minimize noise pick up. to prevent reflections in the scl and sda traces from creating false pulses, the rise and fa ll times of the scl and sda signals must be greater than 20 ns. this can be accomplished by reducing t he drive strength of the i 2 c master via software. the i.mx6 i2c driver defaults to a 40 ohm drive strength. it is recommended to use a drive strength of 80 ohm or higher to increase the edge times. alternatively, this can be accomplished by using small capacitors from scl and sda to ground. for example, use 5.1 pf capacitors from scl and sda to ground for bus pull-up resistors of 4.8 kohm. pwron must be logic high for i 2 c communication to work robustly. 6.5.1 i 2 c device id i 2 c interface protocol requires a device id for addressing the targ et ic on a multi-device bus. to allow flexibility in addressin g for bus conflict avoidance, fuse programmability is provided to al low configuration for the lower 3 address lsb(s). refer to one time programmability (otp) for more details. this product supports 7-bit addressing onl y; support is not provided for 10-bit or general call addressing. note, when the tbb bits for the i 2 c slave address are written, the next access to the chip, must then use the new slave address; these bits take affect right away. 6.5.2 i 2 c operation the i 2 c mode of the interface is implemented generally foll owing the fast mode definition which supports up to 400 kbits/s operation (exceptions to the standard are noted to be 7-bit only addressing and no support for general call addressing.) timing diagrams, electrical specifications, and further details can be found in the i 2 c specification, which is available for download at: http://www.nxp.com/ac robat_download/literat ure/9398/39340011.pdf i 2 c read operations are also performed in byte increments separated by an ack. read op erations also begin with the msb and each b yte will be sent out unless a stop command or nack is received prior to completion. the following examples show how to write and read data to an d from the ic. the host initiates and terminates all communication. the host sends a master command packet after driv ing the start condition. the device will respond to the host if the master command packet contains the corresponding slave address. in the following examples, the device is shown always responding with an ack to transmissions from the host. if at any time a nack is received, the host should terminate the current transaction and retry the transaction. figure 22. i 2 c write example figure 23. i 2 c read example devic e a ddress reg ister addre ss packe t t y pe start r / w host sd a a c k slave sd a a c k m aster driven data ( byte 0) 0 7 stop host can also drive anothe r start instead of stop a c k 0 0 7 0 7 device address register address device address packet type start 0 r/w 16 23 8 15 0 7 a c k stop a c k a c k start 0 7 r/w na ck pmic driven data host can also drive another start instead of stop 1 host sda slave sda
nxp semiconductors 83 pf0200 functional block requirements and behaviors 6.5.3 interrupt handling the system is informed about important events ba sed on interrupts. unmasked interrupt even ts are signaled to the processor by d riving the intb pin low. each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. e ach interrupt can be cleared by writing a ?1? to the appropriate bit in the inte rrupt status register; this will also cause the intb pin to g o high. if there are multiple interrupt bits set the intb pin will remain low until all are either masked or cleared. if a new interrupt occurs while the processor clears an existing interrupt bit, the intb pin will remain low. each interrupt can be masked by setting the corresponding mask bit to a 1. as a result, when a masked interrupt bit goes high, the intb pin will not go low. a masked interrupt can still be read from t he interrupt status register. th is gives the processor the opti on of polling for status from the ic. the ic powers up with all interrupts masked, so the processor mu st initially poll the device to determine i f any interrupts are active. alternatively, the processor can unmask the interrupt bits of interest. if a masked interrupt bit was already high, the intb pin will go low after unmasking. the sense registers contain status and input sense bits so the system processor can poll the current stat e of interrupt sources . they are read only, and not latched or clearable. interrupts generated by external events are debounced; therefore, the ev ent needs to be stable throughout the debounce period b efore an interrupt is generated. nominal debounce periods for each event are documented in the int summary table 100 . due to the asynchronous nature of the debounce timer, t he effective debounce time can vary slightly. 6.5.4 interrupt bit summary table 100 summarizes all interrupt, mask, and sense bi ts associated with intb control. for more detailed behavioral descriptions, refer to the related chapters. table 100. interrupt, mask and sense bits interrupt mask sense purpose trigger debounce time (ms) lowvini lowvinm lowvins low input voltage detect sense is 1 if below 2.80 v threshold h to l 3.9 (74) pwroni pwronm pwrons power on button event h to l 31.25 (74) sense is 1 if pwron is high. l to h 31.25 therm110 therm110m therm110s thermal 110 c threshold sense is 1 if above threshold dual 3.9 therm120 therm120m therm120s thermal 120 c threshold sense is 1 if above threshold dual 3.9 therm125 therm125m therm125s thermal 125 c threshold sense is 1 if above threshold dual 3.9 therm130 therm130m therm130s thermal 130 c threshold sense is 1 if above threshold dual 3.9 sw1afaulti sw1afaultm sw1afaults regulator 1a overcurrent limit sense is 1 if above current limit l to h 8.0 sw1bfaulti sw1bfaultm sw1bfaults regulator 1b overcurrent limit sense is 1 if above current limit l to h 8.0 sw2faulti sw2faultm sw2faults regulator 2 overcurrent limit sense is 1 if above current limit l to h 8.0 sw3afaulti sw3afaultm sw3afaults regulator 3a overcurrent limit sense is 1 if above current limit l to h 8.0 sw3bfaulti sw3bfaultm sw3bfaults regulator 3b overcurrent limit sense is 1 if above current limit l to h 8.0 swbstfaulti swbstfaultm swbstfaults swbst overcurrent limit sense is 1 if above current limit l to h 8.0 vgen1faulti vgen1faultm vgen1faults vgen1 overcurrent limit sense is 1 if above current limit l to h 8.0
84 nxp semiconductors pf0200 functional block requirements and behaviors a full description of all interrupt, mask, and sense registers is provided in tables 101 to 112 . vgen2faulti vgen2faultm vgen2faults vgen2 overcurrent limit sense is 1 if above current limit l to h 8.0 vgen3faulti vgen3faultm vgen3faults vgen3 overcurrent limit sense is 1 if above current limit l to h 8.0 vgen4faulti vgen4faultm vgen4faults vgen4 overcurrent limit sense is 1 if above current limit l to h 8.0 vgen5faulti vgen5faultm vgen1faults vgen5 overcurrent limit sense is 1 if above current limit l to h 8.0 vgen6faulti vgen6faultm vgen6faults vgen6 overcurrent limit sense is 1 if above current limit l to h 8.0 otp_ecci otp_eccm otp_eccs 1 or 2 bit error detected in otp registers sense is 1 if error detected l to h 8.0 notes 74. debounce timing for the falling edge c an be extended with pwrondbnc[1:0]. table 101. register intstat0 - addr 0x05 name bit # r/w default description pwroni 0 r/w1c 0 power on interrupt bit lowvini 1 r/w1c 0 low-voltage interrupt bit therm110i 2 r/w1c 0 110 c thermal interrupt bit therm120i 3 r/w1c 0 120 c thermal interrupt bit therm125i 4 r/w1c 0 125 c thermal interrupt bit therm130i 5 r/w1c 0 130 c thermal interrupt bit unused 7:6 ? 00 unused table 102. register intmask0 - addr 0x06 name bit # r/w default description pwronm 0 r/w1c 1 power on interrupt mask bit lowvinm 1 r/w1c 1 low-voltage interrupt mask bit therm110m 2 r/w1c 1 110 c thermal interrupt mask bit therm120m 3 r/w1c 1 120 c thermal interrupt mask bit therm125m 4 r/w1c 1 125 c thermal interrupt mask bit therm130m 5 r/w1c 1 130 c thermal interrupt mask bit unused 7:6 ? 00 unused table 100. interrupt, mask and sense bits (continued) interrupt mask sense purpose trigger debounce time (ms)
nxp semiconductors 85 pf0200 functional block requirements and behaviors table 103. register intsense0 - addr 0x07 name bit # r/w default description pwrons 0 r 0 power on sense bit 0 = pwron low 1 = pwron high lowvins 1 r 0 low-voltage sense bit 0 = vin > 2.8 v 1 = vin 2.8 v therm110s 2 r 0 110 c thermal sense bit 0 = below threshold 1 = above threshold therm120s 3 r 0 120 c thermal sense bit 0 = below threshold 1 = above threshold therm125s 4 r 0 125 c thermal sense bit 0 = below threshold 1 = above threshold therm130s 5 r 0 130 c thermal sense bit 0 = below threshold 1 = above threshold unused 6 ? 0 unused vddotps 7 r 00 additional vddotp voltage sense pin 0 = vddotp grounded 1 = vddotp to vcoredig or greater table 104. register intstat1 - addr 0x08 name bit # r/w default description sw1afaulti 0 r/w1c 0 sw1a overcurrent interrupt bit sw1bfaulti 1 r/w1c 0 sw1b overcurrent interrupt bit rsvd 2 r/w1c 0 reserved sw2faulti 3 r/w1c 0 sw2 overcurrent interrupt bit sw3afaulti 4 r/w1c 0 sw3a overcurrent interrupt bit sw3bfaulti 5 r/w1c 0 sw3b overcurrent interrupt bit rsvd 6 r/w1c 0 reserved unused 7 ? 0 unused table 105. register intmask1 - addr 0x09 name bit # r/w default description sw1afaultm 0 r/w 1 sw1a overcurrent interrupt mask bit sw1bfaultm 1 r/w 1 sw1b overcurrent interrupt mask bit rsvd 2 r/w 1 reserved sw2faultm 3 r/w 1 sw2 overcurrent interrupt mask bit sw3afaultm 4 r/w 1 sw3a overcurrent interrupt mask bit sw3bfaultm 5 r/w 1 sw3b overcurrent interrupt mask bit rsvd 6 r/w 1 reserved unused 7 ? 0 unused
86 nxp semiconductors pf0200 functional block requirements and behaviors table 106. register intsense1 - addr 0x0a name bit # r/w default description sw1afaults 0 r 0 sw1a overcurrent sense bit 0 = normal operation 1 = above current limit sw1bfaults 1 r 0 sw1b overcurrent sense bit 0 = normal operation 1 = above current limit rsvd 2 r 0 reserved sw2faults 3 r 0 sw2 overcurrent sense bit 0 = normal operation 1 = above current limit sw3afaults 4 r 0 sw3a overcurrent sense bit 0 = normal operation 1 = above current limit sw3bfaults 5 r 0 sw3b overcurrent sense bit 0 = normal operation 1 = above current limit rsvd 6 r 0 reserved unused 7 ? 0 unused table 107. register intstat3 - addr 0x0e name bit # r/w default description swbstfaulti 0 r/w1c 0 swbst overcurrent limit interrupt bit unused 6:1 ? 0x00 unused otp_ecci 7 r/w1c 0 otp error interrupt bit table 108. register intmask3 - addr 0x0f name bit # r/w default description swbstfaultm 0 r/w 1 swbst overcurrent limit interrupt mask bit unused 6:1 ? 0x00 unused otp_eccm 7 r/w 1 otp error interrupt mask bit table 109. register intsense3 - addr 0x10 name bit # r/w default description swbstfaults 0 r 0 swbst overcurrent limit sense bit 0 = normal operation 1 = above current limit unused 6:1 ? 0x00 unused otp_eccs 7 r 0 otp error sense bit 0 = no error detected 1 = otp error detected
nxp semiconductors 87 pf0200 functional block requirements and behaviors table 110. register intstat4 - addr 0x11 name bit # r/w default description vgen1faulti 0 r/w1c 0 vgen1 overcurrent interrupt bit vgen2faulti 1 r/w1c 0 vgen2 overcurrent interrupt bit vgen3faulti 2 r/w1c 0 vgen3 overcurrent interrupt bit vgen4faulti 3 r/w1c 0 vgen4 overcurrent interrupt bit vgen5faulti 4 r/w1c 0 vgen5 overcurrent interrupt bit vgen6faulti 5 r/w1c 0 vgen6 overcurrent interrupt bit unused 7:6 ? 00 unused table 111. register intmask4 - addr 0x12 name bit # r/w default description vgen1faultm 0 r/w 1 vgen1 overcurrent interrupt mask bit vgen2faultm 1 r/w 1 vgen2 overcurrent interrupt mask bit vgen3faultm 2 r/w 1 vgen3 overcurrent interrupt mask bit vgen4faultm 3 r/w 1 vgen4 overcurrent interrupt mask bit vgen5faultm 4 r/w 1 vgen5 overcurrent interrupt mask bit vgen6faultm 5 r/w 1 vgen6 overcurrent interrupt mask bit unused 7:6 ? 00 unused table 112. register intsense4 - addr 0x13 name bit # r/w default description vgen1faults 0 r 0 vgen1 overcurrent sense bit 0 = normal operation 1 = above current limit vgen2faults 1 r 0 vgen2 overcurrent sense bit 0 = normal operation 1 = above current limit vgen3faults 2 r 0 vgen3 overcurrent sense bit 0 = normal operation 1 = above current limit vgen4faults 3 r 0 vgen4 overcurrent sense bit 0 = normal operation 1 = above current limit vgen5faults 4 r 0 vgen5 overcurrent sense bit 0 = normal operation 1 = above current limit vgen6faults 5 r 0 vgen6 overcurrent sense bit 0 = normal operation 1 = above current limit unused 7:6 ? 00 unused
88 nxp semiconductors pf0200 functional block requirements and behaviors 6.5.5 specific registers 6.5.5.1 ic and version identification the ic and other version details can be read via identific ation bits. these are hard-wired on chip and described in tables 113 to 115 . 6.5.5.2 embedded memory there are four register banks of general pur pose embedded memory to store critical data. the data written to mema[7:0], memb[7: 0], memc[7:0], and memd[7:0] is maintained by the coin cell when the main battery is de eply discharged, removed, or contact-bounced . the contents of the embedded memory are reset by coinporb. the banks can be used for any system need for bit retention with coin ce ll backup. table 113. register deviceid - addr 0x00 name bit # r/w default description deviceid 3:0 r 0x01 die version. 0001 = pf0200 unused 7:4 ? 0x01 unused table 114. register silicon rev- addr 0x03 name bit # r/w default description metal_layer_rev 3:0 r xx represents the metal mask revision pass 0.0 = 0000 . . pass 0.15 = 1111 full_layer_rev 7:4 r xx represents the full mask revision pass 1.0 = 0001 . . pass 15.0 = 1111 notes 75. default value depends on the silicon revision. table 115. register fabid - addr 0x04 name bit # r/w default description fin 1:0 r 0x00 allows for characterizing different options within the same reticule fab 3:2 r 0x00 represents the wafer manufacturing facility unused 7:0 r 0x00 unused table 116. register mema addr 0x1c name bit # r/w default description mema 7:0 r/w 0 memory bank a table 117. register memb addr 0x1d name bit # r/w default description memb 7:0 r/w 0 memory bank b
nxp semiconductors 89 pf0200 functional block requirements and behaviors 6.5.6 register bitmap the register map is comprised of thirty-two pages, and its addre ss and data fields are each eight bits wide. only the first two pages can be accessed. on each page, registers 0 to 0x7f are referred to as 'functional' , and registers 0x80 to 0xff as 'extended' . on each page, the functional registers are the same, but the extended registers are different. to access registers on extended page 1 , one must first write 0x01 to the page register at address 0x7f, and to access registers extended page 2 , one must first write 0x02 to the page register at address 0x7f. to access the functional page from one of the extended pages, no writ e to the page register is necessary. registers that are missing in the sequence are reserved; reading from them will return a value 0x00, and writing to them will h ave no effect. the contents of all registers are given in the tables defi ned in this chapter; each table is structure as follows: name: name of the bit. bit #: the bit location in the register (7-0) r/w: read / write access and control ? r is read-only access ? r/w is read and write access ? rw1c is read and write access with write 1 to clear reset: reset signals are color coded based on the following legend. default: the value after reset, as noted in the default column of the memory map. ? fixed defaults are explicitly declared as 0 or 1. ? ?x? corresponds to read / write bits that are initialized at start-up, based on the otp fuse settings or default if vddotp = 1.5 v. bits are subsequently i 2 c modifiable, when their reset has been released. ?x? may also refer to bits that may have other dependencies. for example, some bits may de pend on the version of the ic, or a value fr om an analog block, for instance the sen se bits for the interrupts. table 118. register memc addr 0x1e name bit # r/w default description memc 7:0 r/w 0 memory bank c table 119. register memd addr 0x1f name bit # r/w default description memd 7:0 r/w 0 memory bank d bits reset by sc and vcoredig_porb bits reset by pwron or loaded default or otp configuration bits reset by digresetb bits reset by porb or resetbmcu bits reset by vcoredig_porb bits reset by por or offb
90 nxp semiconductors pf0200 functional block requirements and behaviors 6.5.6.1 register map table 120. functional page bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0 00 deviceid r 8'b0001_0001 ? ? ? ? device id [3:0] 00 0 1 0 0 0 1 03 siliconrevid r 8'b0001_0000 full_layer_rev[3:0] metal_layer_rev[3:0] xx x x x x x x 04 fabid r 8'b0000_0000 ? ? ? ? fab[1:0] fin[1:0] 00 0 0 0 0 0 0 05 intstat0 rw1c 8'b0000_0000 ?? therm130i therm125i therm120i therm110i lowvini pwroni 00 0 0 0 0 0 0 06 intmask0 r/w 8'b0011_1111 ?? therm130m therm125m therm120m therm110m lowvinm pwronm 00 1 1 1 1 1 1 07 intsense0 r 8'b00xx_xxxx vddotps rsvd therm130s therm125s therm120s therm110s lowvins pwrons 00x xxx x x 08 intstat1 rw1c 8'b0000_0000 ? rsvd sw3bfaulti sw3afaulti sw2faulti rsvd sw1bfaulti sw1afaulti 00 0 0 0 0 0 0 09 intmask1 r/w 8'b0111_1111 ? rsvd sw3bfaultm sw3afaultm sw2faultm rsvd sw1bfaultm sw1afaultm 01 1 1 1 1 1 1 0a intsense1 r 8'b0xxx_xxxx ? rsvd sw3bfaults sw3afaults sw2faults rsvd sw1bfaults sw1afaults 0xx xxx x x 0e intstat3 rw1c 8'b0000_0000 otp_ecci ? ? ? ? ? ? swbstfaulti 00 0 0 0 0 0 0 0f intmask3 r/w 8'b1000_0001 otp_eccm ? ? ? ? ? ? swbstfaultm 10 0 0 0 0 0 1 10 intsense3 r 8'b0000_000x otp_eccs ? ? ? ? ? ? swbstfaults 00 0 0 0 0 0 x 11 intstat4 rw1c 8'b0000_0000 ?? vgen6faulti vgen5faulti vgen4faulti vgen3faulti vgen2faulti vgen1faulti 00 0 0 0 0 0 0 12 intmask4 r/w 8'b0011_1111 ?? vgen6 faultm vgen5 faultm vgen4 faultm vgen3 faultm vgen2 faultm vgen1 faultm 00 1 1 1 1 1 1 13 intsense4 r 8'b00xx_xxxx ?? vgen6 faults vgen5 faults vgen4 faults vgen3 faults vgen2 faults vgen1 faults 00x xxx x x 1a coinctl r/w 8'b0000_0000 ?? ? ? coinchen vcoin[2:0] 00 0 0 0 0 0 0
nxp semiconductors 91 pf0200 functional block requirements and behaviors 1b pwrctl r/w 8'b0001_0000 regscpen standbyinv stbydly[1:0] pwronbdbnc[1:0] pwronrsten restarten 00 0 1 0 0 0 0 1c mema r/w 8'b0000_0000 mema[7:0] 00 0 0 0 0 0 0 1d memb r/w 8'b0000_0000 memb[7:0] 00 0 0 0 0 0 0 1e memc r/w 8'b0000_0000 memc[7:0] 00 0 0 0 0 0 0 1f memd r/w 8'b0000_0000 memd[7:0] 00 0 0 0 0 0 0 20 sw1abvolt r/w/m 8'b00xx_xxxx ?? sw1ab[5:0] 00 x x x x x x 21 sw1abstby r/w 8'b00xx_xxxx ?? sw1abstby[5:0] 00 x x x x x x 22 sw1aboff r/w 8'b00xx_xxxx ?? sw1aboff[5:0] 00 x x x x x x 23 sw1abmode r/w 8'b0000_1000 ?? sw1abomode ? sw1abmode[3:0] 00 0 0 1 0 0 0 24 sw1abconf r/w 8'bxx00_xx00 sw1abdvsspeed[1:0] sw1baphase[1:0] sw1abfreq[1:0] ? sw1abilim xx 0 0 x x 0 0 35 sw2volt r/w 8'b0xxx_xxxx ? sw2[6:0] 0x x x x x x x 36 sw2stby r/w 8'b0xxx_xxxx ? sw2stby[6:0] 0x x x x x x x 37 sw2off r/w 8'b0xxx_xxxx ? sw2off[6:0] 0x x x x x x x 38 sw2mode r/w 8'b0000_1000 ?? sw2omode ? sw2mode[3:0] 00 0 0 1 0 0 0 39 sw2conf r/w 8'bxx01_xx00 sw2dvsspeed[1:0] sw2phase[1:0] sw2freq[1:0] ? sw2ilim xx 0 1 x x 0 0 3c sw3avolt r/w 8'b0xxx_xxxx ? sw3a[6:0] 0x x x x x x x 3d sw3astby r/w 8'b0xxx_xxxx ? sw3astby[6:0] 0x x x x x x x 3e sw3aoff r/w 8'b0xxx_xxxx ? sw3aoff[6:0] 0x x x x x x x table 120. functional page (continued) bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0
92 nxp semiconductors pf0200 functional block requirements and behaviors 3f sw3amode r/w 8'b0000_1000 sw3aomode ? sw3amode[3:0] 00 0 0 1 0 0 0 40 sw3aconf r/w 8'bxx10_xx00 sw3advsspeed[1:0] sw3aphase[1:0] sw3afreq[1:0] ? sw3ailim xx 1 0 x x 0 0 43 sw3bvolt r/w 8'b0xxx_xxxx ? sw3b[6:0] 0xx xxx x x 44 sw3bstby r/w 8'b0xxx_xxxx ? sw3bstby[6:0] 0xx xxx x x 45 sw3boff r/w 8'b0xxx_xxxx ? sw3boff[6:0] 0xx xxx x x 46 sw3bmode r/w 8'b0000_1000 ?? sw3bomode ? sw3bmode[3:0] 00 0 0 1 0 0 0 47 sw3bconf r/w 8'bxx10_xx00 sw3bdvsspeed[1:0] sw3bphase[1:0] sw3bfreq[1:0] ? sw3bilim xx 1 0 x x 0 0 66 swbstctl r/w 8'b0xx0_10xx ? swbst1stbymode[1:0] ? swbst1mode[1:0] swbst1volt[1:0] 0x x 0 1 0 x x 6a vrefddrctl r/w 8'b000x_0000 ?? ? vrefddren ? ? ? ? 00 0 x 0 0 0 0 6b vsnvsctl r/w 8'b0000_0xxx ?? ? ? ? vsnvsvolt[2:0] 00 0 0 0 0 x x 6c vgen1ctl r/w 8'b000x_xxxx ? vgen1lpwr vgen1stby vgen1en vgen1[3:0] 000 xxx x x 6d vgen2ctl r/w 8'b000x_xxxx ? vgen2lpwr vgen2stby vgen2en vgen2[3:0] 000 xxx x x 6e vgen3ctl r/w 8'b000x_xxxx ? vgen3lpwr vgen3stby vgen3en vgen3[3:0] 000 xxx x x 6f vgen4ctl r/w 8'b000x_xxxx ? vgen4lpwr vgen4stby vgen4en vgen4[3:0] 000 xxx x x 70 vgen5ctl r/w 8'b000x_xxxx ? vgen5lpwr vgen5stby vgen5en vgen5[3:0] 000 xxx x x 71 vgen6ctl r/w 8'b000x_xxxx ? vgen6lpwr vgen6stby vgen6en vgen6[3:0] 000 xxx x x 7f page register r/w 8'b0000_0000 ?? ? page[4:0] 00 0 0 0 0 0 0 table 120. functional page (continued) bits[7:0] add register name r/w default 7 6 5 4 3 2 1 0
nxp semiconductors 93 pf0200 functional block requirements and behaviors table 121. extended page 1 address register name type default bits[7:0] 7 6 5 4 3 2 1 0 80 otp fuse read en r/w 8'b000x_xxx0 ?? ? ? ??? otp fuse read en 00 0 x xxx0 84 otp load mask r/w 8'b0000_0000 start rl pwbrtn force pwrctl rl pwrctl rl otp rl otp ecc rl otp fuse rl trim fuse 00 0 0 0000 8a otp ecc se1 r 8'bxxx0_0000 ? ? ? ecc5_se ecc4_se ecc3_se ecc2_se ecc1_se xx x 00000 8b otp ecc se2 r 8'bxxx0_0000 ? ? ? ecc10_se ecc9_se ecc8_se ecc7_se ecc6_se xx x 00000 8c otp ecc de1 r 8'bxxx0_0000 ? ? ? ecc5_de ecc4_de ecc3_de ecc2_de ecc1_de xx x 00000 8d otp ecc de2 r 8'bxxx0_0000 ? ? ? ecc10_de ecc9_de ecc8_de ecc7_de ecc6_de xx x 00000 a0 otp sw1ab volt r/w 8'b00xx_xxxx ?? sw1ab_volt[5:0] 00 x x xxxx a1 otp sw1ab seq r/w 8'b000x_xxxx ? sw1ab_seq[4:0] 00 0 x xxxx a2 otp sw1ab config r/w 8'b0000_xxxx ?? ? ? sw1_config[1:0] sw1ab_freq[1:0] 00 0 0 xxxx ac otp sw2 volt r/w 8'b0xxx_xxxx ? sw2_volt[5:0] 0x x x xxxx ad otp sw2 seq r/w 8'b000x_xxxx ?? sw2_seq[4:0] 00 0 x xxxx ae otp sw2 config r/w 8'b0000_00xx ?? ? ? ?? sw2_freq[1:0] 00 0 0 00xx b0 otp sw3a volt r/w 8'b0xxx_xxxx ? sw3a_volt[6:0] 0x x x xxxx b1 otp sw3a seq r/w 8'b000x_xxxx ?? sw3a_seq[4:0] 00 0 x xxxx b2 otp sw3a config r/w 8'b0000_xxxx ?? ? ? sw3_config[1:0] sw3a_freq[1:0] 00 0 0 xxxx
94 nxp semiconductors pf0200 functional block requirements and behaviors b4 otp sw3b volt r/w 8'b0xxx_xxxx ? sw3b_volt[6:0] 0x x x xxxx b5 otp sw3b seq r/w 8'b000x_xxxx ?? sw3b_seq[4:0] 00 0 x xxxx b6 otp sw3b config r/w 8'b0000_00xx ?? ? ? ?? sw3b_config[1:0] 00 0 0 00xx bc otp swbst volt r/w 8'b0000_00xx ?? ? ? ?? swbst_volt[1:0] 00 0 0 00xx bd otp swbst seq r/w 8'b0000_xxxx ?? ? swbst_seq[4:0] 00 0 0 xxxx c0 otp vsnvs volt r/w 8'b0000_0xxx ?? ? ? ? vsnvs_volt[2:0] 00 0 0 00xx c4 otp vrefddr seq r/w 8'b000x_x0xx ?? ? vrefddr_seq[4:0] 00 0 x x0xx c8 otp vgen1 volt r/w 8'b0000_xxxx ?? ? ? vgen1_volt[3:0] 00 0 0 xxxx c9 otp vgen1 seq r/w 8'b000x_xxxx ?? ? vgen1_seq[4:0] 00 0 x xxxx cc otp vgen2 volt r/w 8'b0000_xxxx ?? ? ? vgen2_volt[3:0] 00 0 0 xxxx cd otp vgen2 seq r/w 8'b000x_xxxx ?? ? vgen2_seq[4:0] 00 0 x xxxx d0 otp vgen3 volt r/w 8'b0000_xxxx ?? ? ? vgen3_volt[3:0] 00 0 0 xxxx d1 otp vgen3 seq r/w 8'b000x_xxxx ?? ? vgen3_seq[4:0] 00 0 x xxxx d4 otp vgen4 volt r/w 8'b0000_xxxx ?? ? ? vgen4_volt[3:0] 00 0 0 xxxx d5 otp vgen4 seq r/w 8'b000x_xxxx ?? ? vgen4_seq[4:0] 00 0 x xxxx table 121. extended page 1 (continued) address register name type default bits[7:0] 7 6 5 4 3 2 1 0
nxp semiconductors 95 pf0200 functional block requirements and behaviors d8 otp vgen5 volt r/w 8'b0000_xxxx ?? ? ? vgen5_volt[3:0] 00 0 0 xxxx d9 otp vgen5 seq r/w 8'b000x_xxxx ?? ? vgen5_seq[4:0] 00 0 x xxxx dc otp vgen6 volt r/w 8'b0000_xxxx ?? ? ? vgen6_volt[3:0] 00 0 0 xxxx dd otp vgen6 seq r/w 8'b000x_xxxx ?? ? vgen6_seq[4:0] 00 0 x xxxx e0 otp pu config1 r/w 8'b000x_xxxx ?? ? pwron_ cfg1 swdvs_clk1[1:0] seq_clk_speed1[1:0] 00 0 x xxxx e1 otp pu config2 r/w 8'b000x_xxxx ?? ? pwron_ cfg2 swdvs_clk2[1:0] seq_clk_speed2[1:0] 00 0 x xxxx e2 otp pu config3 r/w 8'b000x_xxxx ?? ? pwron_ cfg3 swdvs_clk3[1:0] seq_clk_speed3[1:0] 00 0 x xxxx e3 otp pu config xor r 8'b000x_xxxx ?? ? pwron_cfg _xor swdvs_clk3_xor seq_clk_speed_xor 00 0 x xxxx e4 (76) otp fuse por1 r/w 8'b0000_00x0 tbb_por soft_fuse_ por ???? fuse_por1 ? 00 0 0 00x0 e5 (76) otp fuse por1 r/w 8'b0000_00x0 rsvd rsvd ? ? ? ? fuse_por2 ? 00 0 0 00x0 e6 (76) otp fuse por1 r/w 8'b0000_00x0 rsvd rsvd ? ? ? ? fuse_por3 ? 00 0 0 00x0 e7 otp fuse por xor r 8'b0000_00x0 rsvd rsvd ? ? ? ? fuse_por_x or ? 00 0 0 00x0 e8 otp pwrgd en r/w/m 8'b0000_000x ?? ? ? ???otp_pg_en 00 0 0 00x0 f0 otp en ecco r/w 8'b000x_xxxx ?? ? en_ecc_ bank5 en_ecc_ bank4 en_ecc_ bank3 en_ecc_ bank2 en_ecc_ bank1 00 0 x xxxx f1 otp en ecc1 r/w 8'b000x_xxxx ?? ? en_ecc_ bank10 en_ecc_ bank9 en_ecc_ bank8 en_ecc_ bank7 en_ecc_ bank6 00 0 x xxxx table 121. extended page 1 (continued) address register name type default bits[7:0] 7 6 5 4 3 2 1 0
96 nxp semiconductors pf0200 functional block requirements and behaviors f4 otp spare2_4 r/w 8'b0000_xxxx ?? ? ? rsvd 00 0 0 xxxx f5 otp spare4_3 r/w 8'b0000_0xxx ?? ? ? ? rsvd 00 0 0 0xxx f6 otp spare6_2 r/w 8'b0000_00xx ?? ? ? ?? rsvd 00 0 0 00xx f7 otp spare7_1 r/w 8'b0000_0xxx ?? ? ? ? ? ? rsvd 00 0 0 0xxx fe otp done r/w 8'b0000_000x ?? ? ? ??? otp_done 00 0 0 000x ff otp i2c addr r/w 8'b0000_0xxx ?? ? ? i2c_slv addr[3] i2c_slv addr[2:0] 00 0 0 1xxx notes 76. in pf0200 it is required to set all of the fu se_porx bits to be able to load the fuses. table 122. extended page 2 address register name type default bits[7:0] 7 6 5 4 3 2 1 0 81 sw1ab pwrstg r/w 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw1ab_pwrstg[2:0] 11 1 11111 84 sw2 pwrstg r 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw2_pwrstg[2:0] 11 1 11111 85 sw3a pwrstg r 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw3a_pwrstg[2:0] 11 1 11111 86 sw3b pwrstg r 8'b1111_1111 rsvd rsvd rsvd rsvd rsvd sw3b_pwrstg[2:0] 11 1 11111 87 pwrctrl r 8'b0111_1111 fslext_ therm_ disable pwrgd_ shdwn_ disable rsvd rsvd rsvd rsvd 00 1 11111 88 pwrctrl otp ctrl r 8'b0000_0001 ?? ? ??? pwrgd_en otp_ shdwn_en 00 0 00001 8d i2c write address trap r/w 8'b0000_0000 i2c_write_address_trap[7:0] 00 0 00000 table 121. extended page 1 (continued) address register name type default bits[7:0] 7 6 5 4 3 2 1 0
nxp semiconductors 97 pf0200 functional block requirements and behaviors 8e i2c trap page r/w 8'b0000_0000 let_it_ roll rsvd rsvd i2c_trap_page[4:0] 00 0 00000 8f i2c trap cntr r/w 8'b0000_0000 i2c_write_address_counter[7:0] 00 0 00000 90 io drv r/w 8'b00xx_xxxx sda_drv[1:0] sdwnb_drv[1:0] intb_drv[1:0] resetbmcu_drv[1:0] 00 x xxxxx do otp auto ecc0 r/w 8'b0000_0000 ?? ? auto_ecc _bank5 auto_ecc _bank4 auto_ecc_b ank3 auto_ecc _bank2 auto_ecc_b ank1 00 0 00000 d1 otp auto ecc1 r/w 8'b0000_0000 ?? ? auto_ecc_b ank10 auto_ecc _bank9 auto_ecc_b ank8 auto_eccba nk7 auto_ecc_b ank6 00 0 00000 d8 (77) reserved ? 8'b0000_0000 rsvd 00 0 00000 d9 (77) reserved ? 8'b0000_0000 rsvd 00 0 00000 e1 otp ecc ctrl1 r/w 8'b0000_0000 ecc1_en_ tbb ecc1_calc_ cin ecc1_cin_tbb[5:0] 00 0 00000 e2 otp ecc ctrl2 r/w 8'b0000_0000 ecc2_en_ tbb ecc2_calc_ cin ecc2_cin_tbb[5:0] 00 0 00000 e3 otp ecc ctrl3 r/w 8'b0000_0000 ecc3_en_ tbb ecc3_calc_ cin ecc3_cin_tbb[5:0] 00 0 00000 e4 otp ecc ctrl4 r/w 8'b0000_0000 ecc4_en_ tbb ecc4_calc_ cin ecc4_cin_tbb[5:0] 00 0 00000 e5 otp ecc ctrl5 r/w 8'b0000_0000 ecc5_en_ tbb ecc5_calc_ cin ecc5_cin_tbb[5:0] 00 0 00000 e6 otp ecc ctrl6 r/w 8'b0000_0000 ecc6_en_ tbb ecc6_calc_ cin ecc6_cin_tbb[5:0] 00 0 00000 e7 otp ecc ctrl7 r/w 8'b0000_0000 ecc7_en_ tbb ecc7_calc_ cin ecc7_cin_tbb[5:0] 00 0 00000 e8 otp ecc ctrl8 r/w 8'b0000_0000 ecc8_en_ tbb ecc8_calc_ cin ecc8_cin_tbb[5:0] 00 0 00000 table 122. extended page 2 (continued) address register name type default bits[7:0] 7 6 5 4 3 2 1 0
98 nxp semiconductors pf0200 functional block requirements and behaviors e9 otp ecc ctrl9 r/w 8'b0000_0000 ecc9_en_ tbb ecc9_calc_ cin ecc9_cin_tbb[5:0] 00 0 00000 ea otp ecc ctrl10 r/w 8'b0000_0000 ecc10_en_t bb ecc10_calc _cin ecc10_cin_tbb[5:0] 00 0 00000 f1 otp fuse ctrl1 r/w 8'b0000_0000 ?? ? ? antifuse1_e n antifuse1_l oad antifuse1_r w bypass1 00 0 0 0 0 00 f2 otp fuse ctrl2 r/w 8'b0000_0000 ?? ? ? antifuse2_e n antifuse2_l oad antifuse2_r w bypass2 00 0 0 0 0 00 f3 otp fuse ctrl3 r/w 8'b0000_0000 ?? ? ? antifuse3_e n antifuse3_l oad antifuse3_r w bypass3 00 0 0 0 0 00 f4 otp fuse ctrl4 r/w 8'b0000_0000 ?? ? ? antifuse4_e n antifuse4_l oad antifuse4_r w bypass4 00 0 0 0 0 00 f5 otp fuse ctrl5 r/w 8'b0000_0000 ?? ? ? antifuse5_e n antifuse5_l oad antifuse5_r w bypass5 00 0 0 0 0 00 f6 otp fuse ctrl6 r/w 8'b0000_0000 ?? ? ? antifuse6_e n antifuse6_l oad antifuse6_r w bypass6 00 0 0 0 0 00 f7 otp fuse ctrl7 r/w 8'b0000_0000 ?? ? ? antifuse7_e n antifuse7_l oad antifuse7_r w bypass7 00 0 0 0 0 00 f8 otp fuse ctrl8 r/w 8'b0000_0000 ?? ? ? antifuse8_e n antifuse8_l oad antifuse8_r w bypass8 00 0 0 0 0 00 f9 otp fuse ctrl9 r/w 8'b0000_0000 ?? ? ? antifuse9_e n antifuse99_ load antifuse9_r w bypass9 00 0 0 0 0 00 fa otp fuse ctrl10 r/w 8'b0000_0000 ?? ? ? antifuse10_ en antifuse10_ load antifuse10_ rw bypass10 00 0 00000 notes 77. do not write in reserved registers. table 122. extended page 2 (continued) address register name type default bits[7:0] 7 6 5 4 3 2 1 0
nxp semiconductors 99 pf0200 typical applications 7 typical applications 7.1 introduction figure 24 provides a typical application diagram of the pf0200 pmic to gether with its functional com ponents. for details on component references and additional components such as filters, refer to the individual sections. 7.1.1 application diagram figure 24. pf0200 typical application schematic vin intb licell swbstfb swbstin swbstlx o/p drive swbst 600 ma boost pwron standby ictest output pin input pin bi-directional pin package pin legend scl sda vddio sw3a/b single phase 2500 ma buck vcoredig vcoreref sdwnb gndref 100nf coin cell battery 1uf 220nf vin 2 x 22uf swbst output 2.2uh 10uf vin to/from ap sw1ain sw1fb sw1alx sw1blx sw1a/b single 2500 ma buck sw1vsssns 1.0uh 4 x 22uf sw1ab output vin 4.7uf vsnvs vsnvs 0.47uf li cell charger resetbmcu sw2 1500 ma buck vgen1 100ma vgen1 vin1 2.2uf vgen2 250ma vgen2 4.7uf vgen3 100ma vgen3 vin2 2.2uf vgen4 350ma vgen4 4.7uf vgen5 100ma vgen5 vin3 2.2uf vgen6 200ma vgen6 2.2uf best of supply otp 100k vrefddr 1uf vddotp vinrefddr vhalf 100nf 100nf vcore 100k 100k 4.7k pf0200 control clocks 32khz and 16mhz initialization state machine i2c interface clocks and resets i2c register map trim-in-package 4.7k 1uf o/p drive o/p drive vin sw1bin 4.7uf sw2fb sw2lx o/p drive sw2in 4.7uf 1.0uh sw2 output 2 x 22uf vin sw2in sw3ain sw3afb sw3alx sw3blx 1.0uh 2 x 22uf sw3a output vin 4.7uf o/p drive o/p drive sw3bin 4.7uf vin sw3b output sw3bfb 2 x 22uf 1.0uh sw3vsssns supplies control dvs control dvs control reference generation sw3a vin core control logic vin1 vin2 vin3 vddotp sw2 sw2 sw2 1.0uf 1.0uf 1.0uf gndref1 vddio to mcu + - 0.1uf
100 nxp semiconductors pf0200 typical applications 7.1.2 bill of materials the following table provides a complete list of the recommende d components on a full featured system using the pf0200 device. c ritical components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components ma y be used. table 123. bill of materials (78) value qty description part# manufacturer component/pin pmic 1 power management ic pf0200 freescale buck, sw1ab - (0.300-1.875 v), 2.5 a 1.0 h1 4 x 4 x 2.1 i sat = 4.5 a for 10% drop, dcr max = 11.9 m xfl4020-102meb coilcraft output inductor 1.0 h? 5 x 5 x 1.5 i sat = 3.6 a for 10% drop, dcr max = 50 m lps5015_102ml coilcraft output inductor (alternate) 1.0 h? 4 x 4 x 1.2 i sat = 6.2 a, dcr = 37 m fdsd0412-h-1r0m toko output inductor (alternate) 0.1 f ? 3 x 3 x 1.5, i sat = 4.5 a, dcr = 39 m 74438335010 wurth elektronik output inductor (alternate) 22 f 4 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 22 f 2 10v, x5r 0805 grm21br61a226me44l murata output capacitance (alternate) 4.7 f 2 10 v x5r 0603 lmk107bj475ka-t t aiyo yuden input capacitance 4.7 f 1 10v x5r 0603 grm155r61a104ka01d murata input capacitance (alternate) 0.1 f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance buck, sw2- (0.400-3.300 v), 1.5 a 1.0 h1 4 x 4 x 1.2 i sat = 2.8 a for 10% drop, dcr max = 60 m lps4012-102nl coilcraft output inductor 1.0 h? 3x 3 1.2 i sat = 2.5 a for 10% drop, dcr max = 42 m xfl3012-102ml coilcraft output inductor (alternate) 1.0 h? 4 x 4 x 1.2 i sat = 6.2 a, dcr = 37 m fdsd0412-h-1r0m toko output inductor (alternate) 0.1 f ? 3 x 3 x 1.5, i sat = 4.5 a, dcr = 39 m 74438335010 wurth elektronik output inductor (alternate) 22 f 2 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 4.7 f 1 10 v x5r 0603 lmk107bj475ka-t t aiyo yuden input capacitance 0.1 f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance buck, sw3ab - (0.400-3.300 v), 2.5 a 1.0 h1 4 x 4 x 2.1 i sat = 4.5 a for 10% drop, dcr max = 11.9 m xfl4020-102meb coilcraft output inductor 1.0 h? 5 x 5 x 1.5 i sat = 3.6 a for 10% drop, dcr max = 50 m lps5015_102ml coilcraft output inductor (alternate)
nxp semiconductors 101 pf0200 typical applications 1.0 h? 4 x 4 x 1.2 i sat = 6.2 a, dcr = 37 m fdsd0412-h-1r0m toko output inductor (alternate) 0.1 f ? 3 x 3 x 1.5, i sat = 4.5 a, dcr = 39 m 74438335010 wurth elektronik output inductor (alternate) 22 f 4 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 4.7 f 2 10 v x5r 0603 lmk107bj475ka-t taiyo yuden input capacitance 0.1 f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance boost, swbst - 5.0 v, 600 ma 2.2 h1 3 x 3 x 1.5 i sat = 2.0 a for 10% drop, dcr max = 110 m lps3015-222ml coilcraft output inductor 2.2 h? 3 x 3 x 1.2 i sat = 3.1 a, dcr = 105 m fdsd0312-h-2r2m toko output inductor (alternate) 2.2 h ? 3 x 3 x 1.5, i sat = 3.5 a, dcr = 94 m 74438335022 wurth elektronik output inductor (alternate) 22 f 2 10 v x5r 0805 lmk212bj226mg-t taiyo yuden output capacitance 10 f 1 10 v x5r 0805 c2012x5r1a106mt tdk input capacitance 2.2 f 1 6.3 v x5r 0402 c0402c225m9pactu kemet input capacitance 0.1 f 1 10 v x5r 0402 c0402c104k8pac kemet input capacitance 1.0 a 1 20 v sod-123fl mbr120vlsft1g on semiconductor schottky diode ldo, vgen1 - (0.80-1.55), 100 ma 2.2 f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance 1.0 f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america input capacitance ldo, vgen2 - (0.80-1.55), 250 ma 4.7 f 1 6.3 v x5r 0402 c0402x5r6r3-475mnp venkel output capacitance ldo, vgen3 - (1.80-3.30), 100 ma 2.2 f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance 1.0 f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america input capacitance ldo, vgen4 - (1.80-3.30), 350 ma 4.7 f 1 6.3 v x5r 0402 c0402x5r6r3-475mnp venkel output capacitance ldo, vgen5 - (1.80-3.30), 150 ma 2.2 f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance 1.0 f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america input capacitance ldo, vgen6 - (1.80-3.30), 200 ma 2.2 f 1 6.3 v x5r 0402 c0402c225m9pactu kemet output capacitance ldo/switch vsnvs - (1.1-3.3), 200 ma 0.47 f 1 6.3 v x5r 0402 c1005x5r0j474k tdk output capacitance reference, vrefddr - (0.20-1.65v), 10 ma 1.0 f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america output capacitance 0.1 f 2 10 v x5r 0402 c0402c104k8pac kemet vhalf, vinrefddr table 123. bill of materials (78) (continued) value qty description part# manufacturer component/pin
102 nxp semiconductors pf0200 typical applications 7.2 pf0200 layout guidelines 7.2.1 general board recommendations 1. it is recommended to use an eight layer board stack-up arranged as follows: ? high current signal ?gnd ? signal ? power ? power ? signal ?gnd ? high current signal 2. allocate top and bottom pcb layers for power rout ing (high-current signals), copper-pour the unused area. 3. use internal layers sandwiched between two gnd planes for the signal routing. 7.2.2 component placement it is desirable to keep all component related to the power stage as close to the pmic as possible, specially decoupling input a nd output capacitors. 7.2.3 general routing requirements 1. some recommended things to keep in mind for manufacturability: ? via in pads require a 4.5 mil minimum annular ring. pad must be 9.0 mils larger than the hole ? maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper ? minimum allowed spacing between line and hole pad is 3.5 mils ? minimum allowed spacing between line and line is 3.0 mils internal references, vcoredig, vcoreref, vcore 1.0 f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america vcoredig 1.0 f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america vcore 0.22 f 1 10 v x5r 0402 grm155r61a224ke19d murata vcoreref coin cell 0.1 f 1 10 v x5r 0402 c0402c104k8pac kemet licell miscellaneous 0.1 f 1 10 v x5r 0402 c0402c104k8pac kemet vddio 1.0 f 1 10 v x5r 0402 cc0402krx5r6bb105 yageo america vin 100 k 1 1/16 w 0402 rk73h1ettp1003f koa speer pwron 100 k 1 1/16 w 0402 rk73h1ettp1003f koa speer resetbmcu 100 k 1 1/16 w 0402 rk73h1ettp1003f koa speer sdwn 100 k 1 1/16 w 0402 rk73h1ettp1003f koa speer intb notes 78. freescale does not assume liability, endorse, or warrant component s from external manufacturers that are referenced in circu it drawings or tables. while freescale offers component recommendati ons in this configuration, it is the cu stomer?s responsibility to validate their a pplication. table 123. bill of materials (78) (continued) value qty description part# manufacturer component/pin
nxp semiconductors 103 pf0200 typical applications 2. care must be taken with swxfb pins traces. these signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the swxin, swx, swxlx, swbstin, swbst, and swbstlx pins. they could be also shielded. 3. shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces). 4. avoid coupling traces between important signal/low noise supplie s (like refcore, vcore, vcoredig) from any switching node (i.e. sw1alx, sw1blx, sw2lx, sw3alx, sw3blx, and swbstlx). 5. make sure that all components related to a specific block are referenced to the corresponding ground. 7.2.4 parallel routing requirements 1. i 2 c signal routing ? clk is the fastest signal of the syst em, so it must be given special care. ? to avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. make sure the ground plane is uniform throughout the whole signal trace length. figure 25. recommended shielding for critical signals ? these signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane. ? care must be taken with these signals no t to contaminate analog signals, as they are high frequency signals. another good practice is to trace them perpendicularly on different laye rs, so there is a minimum area of proximity between signals. 7.2.5 switching regulator layout recommendations 1. per design, the switching regulators in pf0200 are designed to operate with only one input bulk capacitor. however, it is recommended to add a high-frequency filter input capacitor (cin_hf) , to filter out any noise at t he regulator input. this capac itor should be in the range of 100 nf and should be placed right next to or under the ic, closest to the ic pins. 2. make high-current ripple traces low-inductance (short, high w/l ratio). 3. make high-current traces wide or copper islands.
104 nxp semiconductors pf0200 typical applications figure 26. generic buck regulator architecture figure 27. recommended la yout for buck regulators 7.3 thermal information 7.3.1 rating data the thermal rating data of the packages has been simulated with the results listed in table 4 . junction to ambient thermal resistance nomenclatu re: the jedec specification reserves the symbol r ja or ja (theta-ja) strictly for junction-to-ambient thermal resistance on a 1s te st board in natural convection environment. r jma or jma (theta-jma) will be used for both junction-to-ambient on a 2s2p test board in natural convec tion and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. it is anticipated that the generic name, theta-ja, will contin ue to be commonly used. the jedec standards can be consulted at http://www.jedec.org. driver controller swxin swxlx swxfb c out c in l swx vin compensation c in_hf
nxp semiconductors 105 pf0200 typical applications 7.3.2 estimation of jun ction temperature an estimation of the chip junction temperature t j can be obtained from the equation: t j = t a + (r ja x p d ) with: t a = ambient temperature for the package in c r ja = junction to ambient thermal resistance in c/w p d = power dissipation in the package in w the junction to ambient thermal resistance is an industry standard val ue that provides a quick and easy estimation of thermal p erformance. unfortunately, there are two values in common us age: the value determined on a single layer board r ja and the value obtained on a four layer board r jma . actual application pcbs show a performance close to th e simulated four layer board value although this may be somewhat degraded in case of significant power dissipat ed by other components placed close to the device. at a known board temperature, the junction temperature t j is estimated using the following equation t j = t b + (r jb x p d ) with t b = board temperature at the package perimeter in c r jb = junction to board ther mal resistance in c/w p d = power dissipation in the package in w when the heat loss from the package case to the air can be ignor ed, acceptable predictions of j unction temperature can be made. see functional block requirements and behaviors for more details on thermal management.
106 nxp semiconductors pf0200 packaging 8 packaging 8.1 packaging dimensions package dimensions are provided in package drawings. to find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing?s document number. see the thermal characteristics section for specific thermal characteristics for each package. table 124. package drawing information package suffix package outline drawing number 56 qfn 8x8 mm - 0.5 mm pitch. e-type (full lead) ep 98asa00405d 56 qfn 8x8 mm - 0.5 mm pitch. wf -type (wettable flank) es 98asa00589d
nxp semiconductors 107 pf0200 packaging
108 nxp semiconductors pf0200 packaging
nxp semiconductors 109 pf0200 packaging
110 nxp semiconductors pf0200 packaging
nxp semiconductors 111 pf0200 packaging
112 nxp semiconductors pf0200 packaging
nxp semiconductors 113 pf0200 revision history 9 revision history revision date description of changes 3.0 2/2014 ? initial release 4.0 5/2014 ? corrected vddotp maximum rating ? corrected swbstfb maximum rating ? added note to clarify swbst default operation in auto mode ? changed vsnvs current limit ? noted that voltage settings 0.6 v and below are not supported ? vsnvs turn on delay (t d1 ) spec corrected from 15 ms to 5.0 ms 5.0 7/2014 ? updated vtl1, vth1 and vsnvscross threshold specifications ? updated per gpcn 16369 6.0 3/2015 ? added new part number mmpf0200f6aep to the orderable parts table ? added alternative capacitors in bill of materials 8/2016 ? updated to nxp document form and style
information in this document is provided solely to enabl e system and software implementers to use nxp products. there are no expressed or implied copyright licenses grante d hereunder to design or fabricat e any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including withou t limitation, consequential or incidental damages. "typical" parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. n xp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html . how to reach us: home page: nxp.com web support: http://www.nxp.com/support nxp, the nxp logo, freescale, the freescale logo and smartmos are trademarks of nxp b.v. all other product or service names are the property of thei r respective owners. all rights reserved. ? 2016 nxp b.v. document number: mmpf0200 rev. 6.0 8/2016

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